92HD87 Datasheet, PDF (62/204 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD87
SINGLE CHIP PC AUDIO SYSTEM, CODEC+STEREO SPEAKER AMPLIFIER+CAPLESS HP+LDO
Field Name
Rsvd
OD2
OD1
OD0
Bits
R/W
Default
Reset
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2
RW
0h
POR - DAFG - ULR
GPIO2 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float
for 1).
1
RW
0h
POR - DAFG - ULR
GPIO1 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float
for 1).
0
RW
0h
POR - DAFG - ULR
GPIO0 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open-drain (drive 0, float
for 1).
8.3.20. AFG (NID = 01h): DMic
Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8)
Set
Get
F7800h
Byte 1 (Bits 7:0)
778h
Field Name
Rsvd
Mono0
PhAdj
Bits
R/W
Default
Reset
31:5
R
0000000h
N/A (Hard-coded)
Reserved.
4
RW
0h
POR
DMic0 mono select: 0 = stereo operation, 1 = mono operation (left channel du-
plicated to the right channel).
3:2
RW
0h
POR
Selects what phase of the DMic clock the data should be latched:
0h = left data rising edge/right data falling edge
1h = left data center of high/right data center of low
2h = left data falling edge/right data rising edge
3h = left data center of low/right data center of high
IDT CONFIDENTIAL
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©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 0.995 01/11
92HD87