92HD87 Datasheet, PDF (12/204 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD87
SINGLE CHIP PC AUDIO SYSTEM, CODEC+STEREO SPEAKER AMPLIFIER+CAPLESS HP+LDO
Output ports are always on to prevent pops/clicks associated with charging and discharging output
coupling capacitors. This maintains proper bias on output coupling caps even in power state D3 as
long as AVDD is available. Unused ports should be left unconnected. When updating existing
designs to use the codec, ensure that there are no conflicts between the output ports on the codec
and existing circuitry.
AFG Power State
D0-D2
D3
D3cold
D4
D5
Input Enable
1
1
0
0
-
-
-
-
-
Output Enable
1
0
1
0
0
1
-
-
-
Port Behavior
Not allowed. Port is active as output. Input path is mute.
Active - Port enabled as input
Active - Port enabled as output
Inactive -port is powered on (low output impedance) but drives silence only.
Inactive (lower power) - Port keeps output coupling caps charged if port uses caps.
Low power state. If enabled, Beep will output from the port
Inactive (lower power) - Port keeps output coupling caps charged if port uses caps.
Inactive (lower power) - Port keeps output coupling caps charged if port uses caps.
Off - Charge on coupling caps (if used) will not be maintained.
Table 2. Analog Output Port Behavior
2.1.2.
Vref_Out
Ports C & A support Vref_Out pins for biasing electret cartridge microphones. Settings of 80%
AVDD, 50% AVDD, GND, and Hi-Z are supported. Attempting to program a pin widget control with a
reserved or unsupported value will cause the associated Vref_Out pin to assume a Hi-Z state and
the pin widget control Vref_En field will return a value of ‘000’ (Hi-Z) when read.
2.1.3. Jack Detect
Plugs inserted to a jack on Ports A, B, C are detected using SENSE_A. Plugs inserted to a jack on
Ports F, DMIC0, are detected using SENSE_B. Per HDA015-B, the detection circuit operates when
the CODEC is in D0 - D3 and can also operate if both the CODEC and Controller are in D3 (no bus
clock.) Jack detection requires that all supplies (analog and digital) are active and stable. When
AVDD is not present, the value reported in the pin widget is invalid.
When the HD Audio bus is in a low power state (reset asserted and clock stopped) the CODEC will
generate a Power State Change Request when a change in port connectivity is sensed and then
generate an unsolicited response after the HD Audio link has been brought out of a low power state
and the device has been enumerated. Per HDA015-B, this will take less than 10mS.
The following table summarizes the proper resistor tolerances for different analog supply voltages.
AVdd Nominal
Voltage (+/- 5%)
4.75V
Resistor Tolerance
Pull-Up
1%
Resistor Tolerance
SENSE_A/B
1%
Resistor
39.2K
20.0K
10.0K
5.11K
2.49K
SENSE_A
PORT A (HP0)
PORT B (HP1)
PORT C
SENSE_B
NA
PORT F
DMIC0
Pull-up to AVDD Pull-up to AVDD
See reference design for more information on Jack Detect implementation.
IDT CONFIDENTIAL
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©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 0.995 01/11
92HD87