92HD87 Datasheet, PDF (57/204 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD87
SINGLE CHIP PC AUDIO SYSTEM, CODEC+STEREO SPEAKER AMPLIFIER+CAPLESS HP+LDO
Field Name
Rsvd
Data2
Data1
Data0
Bits
R/W
Default
Reset
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2
RW
0h
POR - DAFG - ULR
Data for GPIO2. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
1
RW
0h
POR - DAFG - ULR
Data for GPIO1. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
0
RW
0h
POR - DAFG - ULR
Data for GPIO0. If this GPIO bit is configured as Sticky (edge-sensitive) input,
it can be cleared by writing "0". For details of read back value, refer to HD Audio
spec. section 7.3.3.22
8.3.12. AFG (NID = 01h): GPIOEn
Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8)
Set
Get
F1600h
Byte 1 (Bits 7:0)
716h
Field Name
Rsvd
Mask2
Mask1
Mask0
Bits
R/W
Default
Reset
31:3
R
00000000h
N/A (Hard-coded)
Reserved.
2
RW
0h
POR - DAFG - ULR
Enable for GPIO2: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
1
RW
0h
POR - DAFG - ULR
Enable for GPIO1: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
0
RW
0h
POR - DAFG - ULR
Enable for GPIO0: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
IDT CONFIDENTIAL
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©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 0.995 01/11
92HD87