92HD87 Datasheet, PDF (15/204 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD87
SINGLE CHIP PC AUDIO SYSTEM, CODEC+STEREO SPEAKER AMPLIFIER+CAPLESS HP+LDO
enable this use model, the CODEC must resume within 10mS and not pop. Intel HDA015-B / Low
Power White paper power goals are < 30mW when analog PC_Beep is not enabled, and < 60mW
when analog PC_Beep is enabled. (Charge pump and BTL amplifier power excluded.)
While in AFG D3, the HD Audio controller may be in a D0 state (HD Audio bus active) or in a D3
state (HD Audio bus held in reset with no Bit_Clk, SData_Out, or Sync activity.) The expected behav-
ior is as follows (see the HDA015-B section for more information):
Function
HDA Bus active
HDA Bus stopped
Port Presence Detect
state change
Unsolicited Response
Wake Event¹ followed by an unsolicited response
GPIO state change
Unsolicited Response
Wake Event followed by an unsolicited response
1.The Port Presence detect circuit is currently dependent on a clock and must be changed to gener-
ate a wake event.
2.8.1. AFG D3cold
The D3cold power state is the lowest power state available that does not use vendor specific verbs.
While in D3cold, the CODEC will still respond to bus requests to revert to a higher power state (dou-
ble AFG reset, link reset). However, audio processing, port presence detect, and other functions are
disabled. Per the HD Audio bus HDA015-B, the D3cold state is intended to be used just prior to
removing power to the CODEC. Typically, power will be removed within 200mS. However, the codec
may exit from the D3cold state by generating 2, back-to-back, AFG reset events. Resume time from
D3cold is less than 200mS.
2.9. Vendor Specific Function Group Power States D4/D5
The codec introduces vendor specific power states. A vendor defined verb is added to the Audio
Function Group that combines multiple vendor specific power control bits into logical power states
for use by the audio driver. The 2 states defined offer lower power than the 5 existing states defined
in the HD Audio specification and HDA015-B. The Vendor Specific D4 state provides lower digital
power consumption relative to D3cold by disabling HD Audio link responses. Vendor specific D5 fur-
ther reduces power consumption on the digital supply by turning off GPIO drivers, and reduces ana-
log power consumption by turning off all analog circuitry except for reset circuits.
States D4/D5 are not entered until D3cold has been requested. Software can pre-program the D4 or
D5 state as a re-definition of how the part will behave when the D3cold power state is requested or
software may enter D3cold, then set the D4 or D5. The preferred method is to request D3cold, then
select D4 or D5 as desired.This will reduce the severity of pops encountered when entering D4 or
D5.
Both power states require a link reset or removal of DVDD to exit.
The CODEC may pop when using these verbs and transition times to an active state (D1 or D0 for
example) may take several seconds.
2.10. Low-voltage HDA Signaling
The codec is compatible with either 1.5V or 3.3V HDA bus signaling; the voltage selection is done
dynamically based on the input voltage of DVDD_IO.
DVDD_IO is currently not a logic configuration pin, but rather provides the digital power supply to be
used for the HDA bus signals.
IDT CONFIDENTIAL
15
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 0.995 01/11
92HD87