92HD87 Datasheet, PDF (38/204 Pages) Integrated Device Technology – SINGLE CHIP PC AUDIO SYSTEM

92HD87
SINGLE CHIP PC AUDIO SYSTEM, CODEC+STEREO SPEAKER AMPLIFIER+CAPLESS HP+LDO
9.Spurious tone rejection is tested with ADC dither enabled and compared to ADC performance without dither.
10.All functions/converters active, pin complexes enabled, two FDX streams, line (10Kohm) loads. Add 24mA analog current per
stereo 32 ohm headphone.
11.One stereo DAC and corresponding pin widgets enabled (playback mode)
12.Mixer enabled
13.Idle measurement D3 set for minimum clicks/pops (biases and min. amps. on)
14.Can be set to 0.5 or 0.8 AVdd.
3.3. AC Timing Specs
3.3.1. HD Audio Bus Timing
Parameter
Definition
Symbol
BCLK Frequency
Average BCLK frequency
BCLK Period
BCLK High Phase
BCLK Low Phase
BCLK jitter
SDI delay
SDO setup
SDO hold
Period of BCLK including jitter
Tcyc
High phase of BCLK
T_high
Low phase of BCLK
T_low
BCLK jitter
Time after rising edge of BCLK
that SDI becomes valid
T_tco
Setup for SDO at both rising and
falling edges of BCLK
T_su
Hold for SDO at both rising and
falling edges of BCLK
T_h
Table 14. HD Audio Bus Timing
Figure 7. HD Audio Bus Timing
Min
23.997
6
41.163
17.5
17.5
Typ
24.0
41.67
150
Max
24.002
4
42.171
24.16
24.16
500
Units
Mhz
ns
ns
ns
ps
3
11
ns
5
ns
5
ns
IDT CONFIDENTIAL
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©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
V 0.995 01/11
92HD87