9VRS4339B Datasheet, PDF (3/21 Pages) Integrated Device Technology – VERY LOW POWER CLOCK FOR 2011 NETBOOKS

9VRS4339B
VERY LOW POWER CLOCK FOR 2011 NETBOOKS
Pin Descriptions (cont.)
29 GNDSATA
30 SATA#_LPRS
31 SATA_LPRS
32 SRC4#_LPRS
33 SRC4_LPRS
34 VDDSRC_LVIO
35 PCI_STOP#_3.3
36 SRC3#_LPRS
37 SRC3_LPRS
38 SRC6#_LPRS
39 SRC6_LPRS
40 GNDSRC
41 SRC2#_LPRS
42 SRC2_LPRS
43 SRC#7_LPRS
44 SRC7_LPRS
45 CPU_STOP#_3.3
46 CPU_ITP#/SRC1#_LPRS
47 CPU_ITP/SRC1_LPRS
48 VDD_CORE_1.5
49 VDDCPU_LVIO
50 CPU1#_LPRS
51 CPU1_LPRS
52 GNDCPU
53 CPU0#_LPRS
54 CPU0_LPRS
55 CLKPWRGD/PD#_3.3
56 GND25
PWR
OUT
OUT
OUT
OUT
PWR
IN
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
PWR
OUT
OUT
IN
PWR
Ground pin for the SATA outputs
Complementary clock of low power differential push-pull SATA clock pair with
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.
True clock of low power differential push-pull SATA clock pair with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
Power pin for SRC I/O, nominally 1.05V to 1.5V from external power supply
Stops all stoppable PCI, SATA and SRC clocks when low. Free-Running PCI, SATA
and SRC clocks are not effected by this input. This input is 3.3V tolerant.
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
Ground pin for the SRC outputs
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
Stops all stoppable CPU clocks when enabled. This is a 3.3V tolerant input.
Complementary clock of low power differential CPU_ITP/SRC pair with integrated
33ohm series resistor. No 50ohm resistor to GND needed. The pin function is
determined by the latched value on ITP_EN:
0 = SRC1#
1 = CPU_ITP#
True clock of low power differential CPU_ITP/SRC pair with integrated 33ohm series
resistor. No 50ohm resistor to GND needed. The pin function is determined by the
latched value on ITP_EN:
0 = SRC1
1 = CPU_ITP
Power pin for core PLL, nominal 1.5V
Power pin for CPU I/O, nominally 1.05V to 1.5V from external power supply
Complementary clock of differential pair 0.8V push-pull CPU output with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU output with integrated 33ohm series
resistor. No 50 ohm resistor to GND needed.
Ground pin for the CPU outputs
Complementary clock of differential pair 0.8V push-pull CPU output with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU output with integrated 33ohm series
resistor. No 50 ohm resistor to GND needed.
This 3.3V LVTTL input notifies device to sample latched inputs and start up on first
high assertion or exit Power Down Mode on subsequent assertions. When WLAN
enable in Byte13 bit 5 =1, device will enter Wake-On-LAN mode with 25MHz being
free-running.
1 = Normal operation
0 = Power Down Mode or Wake-On-LAN mode
Note: For lowest power saving during WOL mode, it is mandatory to connect 3.3V
and 1.5V core VDD pins to standby power and suspend/remove VDDIO pins.
Ground pin for 25MHz
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS
3
9VRS4339B
REV A 010312