9VRS4339B Datasheet, PDF (11/21 Pages) Integrated Device Technology – VERY LOW POWER CLOCK FOR 2011 NETBOOKS

9VRS4339B
VERY LOW POWER CLOCK FOR 2011 NETBOOKS
Absolute Maximum Ratings–DC Parameters
Stresses above the ratings listed below can cause permanent damage to the 9VRS4339B. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX UNITS Notes
Maximum Supply Voltage
VDD27, VDD_3.3
Supply Voltage
4.6
V
1,4
Maximum Supply Voltage
VDD_CORE_1.5
Supply Voltage
1.9
V
1,4
Maximum Supply Voltage
VDD_LVIO
Supply Voltage
1.9
V
1,4
Maximum Input Voltage
VIH
3.3V Inputs, including SMBus
4.6
V
1,2,4
Minimum Input Voltage
VIL
Any Input
GND - 0.5
V
1,4
Storage Temperature
Ts
-
-65
150
°_C
4
Case Temperature
Tcase
-
115
°C
1
Input ESD protection
ESD prot
Human Body Model
2000
V
3,4
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1 _{Intentionally blank}
2 _{Maximum VIH is not to exceed VDD}
3 _{Human Body Model}
4 _{Operation under these conditions is neither implied, nor guaranteed.}
Electrical Characteristics–PCICLK/PCICLK_F
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX UNITS
Long Accuracy
pp m
see Tperiod min-max values
-100
10 0
ppm
Clock period
T_{peri od}
33.33MHz output no spread
33.33MHz output spread
29.99700 30.00300 ns
30.08421 30.23459 ns
Absolute min/ma x period
T _{a bs}
33.33MHz output no spread
33.33MHz output nominal/spread
29.49700 30.50300 ns
29.56617 30.58421 ns
Output High Voltage
V_OH
I_OH = -1 mA
2.4
V
Output Low Voltage
V_OL
I_OL = 1 mA
0.4
V
Output High Current
I_OH
V _OH @MIN = 1.0 V
V_OH@MAX = 3 .135 V
- 33
mA
-3 3
mA
Output Low Current
Rising Edge Slew Rate
I_OL
VOL @ MIN = 1.95 V
V_OL @ MAX = 0.4 V
30
mA
38
mA
t_{SL R}
Measu red from 0.8 to 2 .0 V
1
4
V /ns
Falling E dge Slew Rate
Duty Cycle
t _{FL R}
Measu red from 2.0 to 0 .8 V
1
4
V /ns
d_t1
V_T = 1.5 V
45
55
%
Adjacent Pin to Pin Skew
t_{sk ew}
V_T = 1.5 V, PCI Aligned Mode (Default)
25 0
ps
Adjacent P in to Pin Intentional Dela y
t_{s kew_ de lay}
Total PCI Skew Window
t_{ske w_to ta l}
Jitter, Cycle to cycle
t_{j cyc-cyc}
*TA = 0 - 70°C; Sup ply Voltage VDD = 3.3 V +/-5%, Rs=39ohm, CL=5 pF
V_T = 1.5 V, PCI Delayed Mode
V_T = 1.5 V , PCI Delaye d Mode
V_T = 1.5 V
200ps typical
ps
800
ps
50 0
ps
1 _{Unless otherwise noted, gu aranteed by design and ch aracterization, no t 100% teste d in prod uction.}
2 _{All Long Term Accuracy and Clo ck Pe riod spe cifica tions are guaranteed assuming that REFOUT is at 25.0000 00MHz}
3_{Edge rate in system is measured from 0.8V to 2.0V.}
4 _{Duty cycle, Peroid , Ske w and Jitte r ar e measured with respect to 1.5V}
5 _{The ave rage period over any 1us period of time}
6 _{Usin g freque ncy coun ter with th e measurment in terval equal or greater tha t 0.1 5s. Target frequ encie s are 14.318181 MHz, 25.0000 00MHz, 33.33333 3MHz,}
27.000000MHz an d 48 .000 000MHz
7 _{Adja cent pin to pin skew is the pin to pin skew between PCI1 and PCI2 , PCI2 and PCI3, or PCI3 to P CI4.}
8 _{Adja cent pin to pin inte ntio nal d elay is the inte ntion al d elay between PCI1 and PCI2, PCI2 and PCI3 , or PCI3 to PCI4.}
9 _{Total PCI ske w win odw is ab solute skew be tween PCI1 and PCI4.}
NOTES
1,2
1,2,5
1,2,5
1,2
1,2
1
1
1
1
1
1
1,3
1,3
1,4
1,4,7
1,4,8
1,4,9
1,4
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS
11
9VRS4339B
REV A 010312