9VRS4339B Datasheet, PDF (10/21 Pages) Integrated Device Technology – VERY LOW POWER CLOCK FOR 2011 NETBOOKS

9VRS4339B
VERY LOW POWER CLOCK FOR 2011 NETBOOKS
SMBus Table: Output Control Register
Byte 11
Name
Bit 7
Bit 6
Bit 5
Bit 4
CPU
SRC
SATA
DOT96
Bit 3
Bit 2
PCI2
Bit 1
Bit 0
PCI1
Control Function
Differential Slew Rate
Differential Slew Rate
Differential Slew Rate
Differential Slew Rate
Slew Rate Control
Slew Rate Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
0=2.5V/ns
0=2.5V/ns
0=2.5V/ns
0=2.5V/ns
00 = 1.5V/ns
10 = 2.6V/ns
00 = 1.5V/ns
10 = 2.6V/ns
1
1=4V/ns
1=4V/ns
1=4V/ns
1=4V/ns
01 = 2.0V/ns
11 = 3.3V/ns
01 = 2.0V/ns
11 = 3.3V/ns
Default
1
1
1
1
0
0
0
0
SMBus Table: M/N Enable & Output Stop Control Register
Byte 12
Name
Control Function
Bit 7
CPU/SRC PLL M/N En
Enables M/N programming for
CPU/SRC PLL
Bit 6
Bit 5
SRC1 STOP EN
SRC2 STOP EN
Enables Control of SRC1 with
PCI_STOP
Enables Control of SRC2 with
PCI_STOP
Bit 4
SRC3 STOP EN
Enables Control of SRC3 with
PCI_STOP
Bit 3
Bit 2
SRC4 STOP EN
SRC5 STOP EN
Enables Control of SRC4 with
PCI_STOP
Enables Control of SRC5 with
PCI_STOP
Bit 1
SRC6 STOP EN
Enables Control of SRC6 with
PCI_STOP
Bit 0
SRC7 STOP EN
Enables Control of SRC7 with
PCI_STOP
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
1
Enable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Default
0
0
0
0
0
0
0
0
SMBus Table: Output Control Register
Byte 13
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
ITP_EN
SEL_PCI
WOL Enable
PCI_F1
PCI2
PCI3
PCI4
SATA STOP EN
Control Function
ITP_EN readback
Select PCI Readback
WOL Enable for 25M
Free Running with PCI_STOP#
Free Running with PCI_STOP#
Free Running with PCI_STOP#
Free Running with PCI_STOP#
Enables Control of SATA with
PCI_STOP
Type
R
R
RW
RW
RW
RW
RW
RW
0
SRC1
27M
WOL Disabled
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
1
CPU_ITP
PCI4
WOL Enabled
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Default
Latch
Latch
1
0
1
1
1
0
* For lowest power saving during WOL mode, it is mandatory to connect 3.3V and 1.5V core VDD pins to standby power
and suspend/remove VDDIO pins.
SMBus Table: Differential Output Amplitude Control Register
Byte 14
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Name
PCIEX_AMP<1>
PCIEX_AMP<0>
DOT96_AMP<1>
DOT96_AMP<0>
SATA_AMP<1>
SATA_AMP<0>
Control Function
PCIEX Amplitude Control bit1
PCIEX Amplitude Control bit0
DOT96 Amplitude Control bit1
DOT96 Amplitude Control bit0
SATA Amplitude Control bit1
SATA Amplitude Control bit0
Type
RW
RW
RW
RW
RW
RW
Bit 1
CPU_AMP<1>
CPUCLK Amplitude Control bit1 RW
0
00 = 700mV
10 = 900mV
00 = 700mV
10 = 900mV
00 = 700mV
10 = 900mV
00 = 700mV
1
01 = 800mV
11 = 1000mV
01 = 800mV
11 = 1000mV
01 = 800mV
11 = 1000mV
01 = 800mV
Default
0
1
0
1
0
1
0
Bit 0
CPU_AMP<0>
CPUCLK Amplitude Control bit0 RW
10 = 900mV
11 = 1000mV
1
Bytes 15+ Reserved Registers
************************************************************************************************************************************************************************
All reserved bits and reserved bytes in this SMBus table should not be overwritten at any instance. Writing to these reserved
bits and bytes may cause unexpected behavior. IDT does not warrant any application issue going forward if continuing to
overwrite these reserve bits and bytes.
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS
10
9VRS4339B
REV A 010312