9VRS4339B Datasheet, PDF (16/21 Pages) Integrated Device Technology – VERY LOW POWER CLOCK FOR 2011 NETBOOKS

9VRS4339B
VERY LOW POWER CLOCK FOR 2011 NETBOOKS
Electrical Characteristics–27MHz
PAR AM ETE R
SYMBOL
CONDITIONS
MIN
MAX UNITS
Long Accuracy
ppm
see Tperiod min-max values
- 50
50
ppm
- 15
15
ppm
Clock period
T_{p eri od}
27.000MHz output nominal
37.0365 37.0376
ns
Output High Voltage
V_OH
I_OH = -1 mA
2.4
V
Output Low Voltage
V_OL
I_OL = 1 mA
0.4
V
Output High Current
IOH
V _OH @MIN = 1.0 V
VOH@MAX = 3 .135 V
- 29
mA
-2 3
mA
Output Low Current
I_OL
V_OL @ MIN = 1.95 V
V_OL @ MAX = 0.4 V
29
mA
27
mA
Rising Edge Slew Rate
t_{SL R}
Measu red from 0.8 to 2 .0 V
1
4
V /ns
Falling E dge Slew Rate
t _{FL R}
Measu red from 2.0 to 0 .8 V
1
4
V /ns
Duty Cycle
d_t1
V_T = 1.5 V
45
55
%
Jit te r
t_{l tj}
t_{j cyc-cyc}
Long Term (10us), , V_T = 1.5 V
Cycle to Cycle, V_T = 1.5 V
400
ps
200
ps
*TA = 0 - 70°C; Sup ply Voltage VDD = 3.3 V +/-5%, Rs = 39ohm, CL = 5pF
1 _{Unless otherwise noted, gu aranteed by design and ch aracterization, no t 100% teste d in prod uction.}
2 _{All Long Term Accuracy and Clo ck Pe riod spe cifica tions are guaranteed assuming that REFOUT is at 25.0000 00MHz}
3_{Edge rate in system is measured from 0.8V to 2.0V.}
4 _{Duty cycle, Peroid and Jitter are me asur ed with re spe ct to 1.5V}
5 _{The ave rage period over any 1us period of time}
6 _{Usin g freque ncy coun ter with th e measurment in terval equal or greater tha t 0.1 5s. Target frequ encie s are 14.318181 MHz, 25.0000 00MHz, 33.33333 3MHz,}
27.000000MHz an d 48 .000 000MHz
7 _{At n omin al voltage and temper atur e.}
Notes
1,2
1,2,7
1,4,5
1
1
1
1
1
1
1,3
1,3
1,4
1,4
1,4
Clock Jitter Specifications - Low Power Differential Outputs
P ARAM ET ER
SY MBOL
CONDITIONS
MIN
MAX UNITS NOTES
PCIEX Ph ase Jitter
t_{jp ha sePLL}
t_{jp ha seLo}
PCIe Gen 1
PCIe Gen 2
10kHz < f < 1.5MHz
86
ps (p-p) 1,2
3.0 ps (RMS) 1,3,4
t_{jp ha seH igh}
PCIe Gen 2
1.5MHz < f < Nyquist (50MHz)
3.1 ps (RMS) 1,3,4
*TA = 0 - 70°C; Sup ply Voltage VDD = 1.5 V +/- 5%, Rs=0ohm, CL=2p F
1 _{Unless otherwi se noted, guaranteed by design and characterization, not 100% tested in production.}
2_{JItter specs are specifie d as measured on a clock characterizatio n bo ard. System designers need to take special care not to use these numbers, as th e in- system}
3 _{Phase ji tter requirement: The designated G en2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base Spec. The test is performed}
4_{S ee h ttp://www.pcisig .com for complete spe cs}
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS
16
9VRS4339B
REV A 010312