9VRS4339B Datasheet, PDF (2/21 Pages) Integrated Device Technology – VERY LOW POWER CLOCK FOR 2011 NETBOOKS

9VRS4339B
VERY LOW POWER CLOCK FOR 2011 NETBOOKS
Pin Descriptions
PIN #
PIN NAME
1 X2
2 X1
3 VDD25_3.3
4 25M
5 SDATA_3.3
6 SCLK_3.3
7 VDDPCI_3.3
8 vITP_EN/PCI_F1_2x
9 FSLB/PCI2_2x
10 CLKREQA#/PCI3_2x
11 GNDPCI
12 GND14M
13 14M_2X/FSLC
14 VDD14_3.3
15 VDD48_3.3
16 ^DOT96_SEL/USB48M
17 CLKREQC#/48M
18 GND48
19 CLKREQB#
20 VDD27
21 vSEL_PCI/27M_PCI4_2X
22 GND27
23 DOT96_LPRS/SRC5_LPRS
24 DOT96#_LPRS/SRC5#_LPRS
25 VDD_CORE_1.5
26 LCD100_LPRS
27 LCD100#_LPRS
28 GNDLCD
TYPE
OUT
IN
PWR
OUT
I/O
OUT
PWR
I/O
I/O
I/O
PWR
PWR
I/O
PWR
PWR
I/O
I/O
PWR
IN
PWR
I/O
PWR
OUT
OUT
PWR
OUT
OUT
PWR
DESCRIPTION
Crystal output, nominally 25MHz
Crystal input, nominally 25MHz
Power pin for crystal and 25MHz output, nominal 3.3V
3.3V 25MHz clock output
Data pin for SMBus circuitry, 3.3V tolerant.
Clock pin of SMBus circuitry, 3.3V tolerant.
Power supply for PCI clocks, nominal 3.3V
ITP enable latched input
ITP_Enable Selects the functionality of the CPU_ITP/SRC output as follows:
1 = CPU_ITP output
0 = SRC1 output
/ Free-Running 3.3V PCI clock output, default to drive 2 loads.
3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see
input electrical characteristics for Vil_FS and Vih_FS values / 3.3V PCI clock output,
default to drive 2 loads.
3.3V real-time output enable for PCI Express (SRC) outputs. SMBus selects which
outputs are controlled. Pin function is programmable through SMBus. See
CLKREQ# Control Table and SRC Power Management Table for details
0 = controlled outputs are enabled
1 = controlled outputs are Low/Low
/ 3.3V PCI clock output, default to drive 2 loads. .
Ground pin for the PCI outputs
Ground pin for the 14.318MHz output
3.3V 14.318 MHz clock output, default to drive 2 loads / 3.3V tolerant input for CPU
frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values.
Power pin for 14.318MHz output, nominal 3.3V
Power pin for 48MHz outputs, nominal 3.3V
Input latched pin to select Pin23/24 as DOT 96MHz clock or SRC clock
1 = DOT96 output
0 = SRC5 output
/ 3.3V 48MHz USB clock output.
3.3V real-time output enable for PCI Express (SRC) outputs. SMBus selects which
outputs are controlled. Pin function is programmable through SMBus. See
CLKREQ# Control Table and SRC Power Management Table for details
0 = controlled outputs are enabled
1 = controlled outputs are Low/Low
/ 3.3V 48MHz clock output
Ground pin for 48MHz outputs
3.3V real-time output enable for PCI Express (SRC) outputs. SMBus selects which
outputs are controlled.
0 = controlled outputs are enabled
1 = controlled outputs are Low/Low
Power pin for 27MHz output , nominal 3.3V
3.3V input latch pin to select this pin as 27M output or PCI4 clock output. This pin has
an internal pulldown resistor. Latch functionality is as follows:
0 = 27MHz output
1 = 33.33MHz PCI output
Ground pin for the 27MHz output
True clock of push-pull DOT96 or SRC clock with integrated series resistor. No 50
ohm pull down needed. Default is pending on Pin16 DOT96_SEL.
Complement clock of push-pull DOT96 or SRC clock with integrated series resistor.
No 50 ohm pull down needed. Default is pending on Pin16 DOT96_SEL.
Power pin for core PLL's, nominal 1.5V.
True clock of differential push-pull LCD100 output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
Complementary clock of differential push-pull LCD100 output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
Ground pin for LCD clock output
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS
2
9VRS4339B
REV A 010312