9VRS4339B Datasheet, PDF (13/21 Pages) Integrated Device Technology – VERY LOW POWER CLOCK FOR 2011 NETBOOKS

9VRS4339B
VERY LOW POWER CLOCK FOR 2011 NETBOOKS
Electrical Characteristics–Input/Supply/Common Output DC Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX UNITS Notes
Ambient Operating Temp
Tambient
-
0
70
°C
Supply Voltage
VDD27, VDD_3.3
VDD_CORE_1.5
Supply Voltage
Supply Voltage
3.135
3.465
V
1.425
1.575
V
VDD_LVIO
Supply Voltage
0.9975
1.575
V
Input High Voltage
VIHSE
Single-ended 3.3V inputs
2
VDD + 0.3
V
3
Input Low Voltage
VILSE
Single-ended 3.3V inputs
VSS - 0.3
0.8
V
3
Latched Input High Voltage
VIH_LI
Single-ended 3.3V Latched Inputs
2
VDD + 0.3 V
Latched Input Low Voltage
VIL_LI
Single-ended 3.3V Latched Inputs
VSS - 0.3
0.8
V
Low Threshold Latched Input-
High Voltage
VIH_FS
Low threshold inputs FSL[C:B]
0.7
VDD+0.3 V
Low Threshold Latched Input-
Low Voltage
VIL_FS
Low threshold inputs FSL[C:B]
VSS - 0.3
0.35
V
Input Leakage Current
IIN
VIN = VDD , VIN = GND
-5
5
uA
2
Input Leakage Current
IINRES
Inputs with pull up or pull down resistors
VIN = VDD , VIN = GND
-200
200
uA
Output High Voltage
VOHSE
Single-ended outputs, IOH = -1mA
2.4
V
1
Output Low Voltage
VOLSE
Single-ended outputs, IOL = 1 mA
0.4
V
1
IDDOP3.3
Full Active, CL = Full load; IDD 3.3V
38
mA
Operating Supply Current
IDDOP1.5
Full Active, CL = Full load; IDD 1.5V
40
mA
IDDOP1.05
Full Active, CL = Full load; IDD LVIO
46
mA
IDDPD3.3
Power down mode, 3.3V Rail
1.2
mA
5
Powerdown Current
IDDPD1.5
Power down mode, 1.5V Rail
1
mA
5
IDDPDLVIO
Power down mode, 1.05V Rail
0
mA
5
IDDWOL3.3
Wake On LAN mode, 3.3V Rail
10
mA
6
Wake-On-Lan Current
IDDWOL1.5
Wake On LAN mode, 1.5V Rail
1
mA
6
IDDWOLLVIO
Wake On LAN mode, LVIO Rail
0
mA
6
Input Frequency
Fi
VDD = 3.3 V
25MHz Typical
MHz
4
Pin Inductance
Lpin
7
nH
CIN
Logic Inputs
1.5
5
pF
Input Capacitance
COUT
Output pin capacitance
6
pF
CINX
X1 & X2 pins
6
pF
Clk Stabilization
TSTAB
From VDD Power-Up or de-assertion of PD
to 1st clock
1.8
ms
Tstop_CR_off
TCROFF
Output stop after CLKREQ# deasserted
2
3
Clocks
Trun_CR_on
TCRON
Output run after CLKREQ# asserted
2
3
Clocks
Tstop
TSTOP
CPU or PCI stop after
CPU or PCI STOP# assertion
2
3
Clocks
Trun
TRUN
CPU or PCI run after
CPU or PCI STOP# de-assertion
2
3
Clocks
Tfall_SE
Trise_SE
TFALL
TRISE
Fall/rise time of all 3.3V control inputs from 20-
80%
10
ns
10
ns
SMBus Voltage
VDD
2.7
3.3
V
Low-level Output Voltage
Current sinking at
VOLSMB = 0.4 V
VOLSMB
IPULLUP
@ IPULLUP
SMB Data Pin
0.4
V
4
mA
SCLK/SDATA
Clock/Data Rise Time
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
SCLK/SDATA
Clock/Data Fall Time
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
Maximum SMBus Operating Frequency
FSMBUS
100
kHz
Spread Spectrum Modulation Frequency
fSSMOD
Triangular Modulation
30
33
kHz
NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1_{Signal is required to be monotonic in this region.}
2 _{input leakage current does not include inputs with pull-up or pull-down resistors}
3 _{3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, ITP_EN, SCLK, SDATA, CLKPWRGD/PD#, DOT96_SEL, SEL_PCI, 48M_SEL and PEREQ# inputs if}
selected.
4 _{For margining purposes only. Normal operation should have Fin = 25MHz +/-50ppm}
5 _{Standard powerdown with Wake on LAN disabled.}
6 _{Powerdown with Wake on LAN enabled}
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS
13
9VRS4339B
REV A 010312