IC42S16160 Datasheet, PDF (61/69 Pages) Integrated Circuit Solution Inc – 4M x 16Bit x 4 Banks (256-MBIT) SDRAM

IC42S16160
Full Page Read Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE High
tCK3
CS
RAS
CAS
WE
*BS0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
Hi-Z
DQ
Activate
Command
Bank A
QAa QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa0 QBa+1 QBa+2 QBa+3 QBa+4 QBa+5
Read
Command
Bank A
Activate
Command
Bank B
Read ^{Full page burst operation}
Command
Bank B
does not teminate when
the burst length is satisfied;
the burst counter increments
and continues bursting
The burst counter wraps _{beginning with the starting}
from the highest order _address
page address back to zero
during this time interval
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
BS1=”L”, Bank C,D = Idle
Integrated Circuit Solution Inc.
61
DR037-0A 9/05/2003