IC42S16160 Datasheet, PDF (27/69 Pages) Integrated Circuit Solution Inc – 4M x 16Bit x 4 Banks (256-MBIT) SDRAM

IC42S16160
PRECHARGE TERMINATION
PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
When CAS latency is 2, the read data will remain valid until one clock after the precharge command.
When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
CLK
Command
CAS latency=2
DQ
Burst lengh= X
T0
T1
T2
T3
T4
T5
T6
T7
T8
Read
PRE
t_RP
ACT
Q0
Q1
Q2
Q3
Hi-Z
command
CAS latency=3
DQ
Read
PRE
Q0
Q1
t_RP
Q2
Q3
ACT
Hi-Z
Integrated Circuit Solution Inc.
27
DR037-0A 9/05/2003