IC42S16160 Datasheet, PDF (14/69 Pages) Integrated Circuit Solution Inc – 4M x 16Bit x 4 Banks (256-MBIT) SDRAM

IC42S16160
OPERATION COMMAND TABLE^(continue)
Current State Command
Operation
CS RAS CAS WE Address
Write
DESL
Nop -> Enter precharge after tDPL
H X X XX
recovering
NOP
Nop -> Enter precharge after tDPL
L H H HX
with auto
BST
Nop -> Enter precharge after tDPL
L H H LX
precharge
READ/READA
Illegal^{(3 ,8, 11)}
L H L H BA, CA, A10
WRIT/WRITA
Illegal^(3,11)
L H L L BA, CA, A10
ACT
Illegal^{(3, 11)}
L L H H BR, RA
PRE/PALL
Illegal^{(3, 11)}
L L H L BA, A10
REF/SELF
Illegal
L L L HX
MRS
Illegal
L
L
L
L Op-Code
Auto
DESL
Nop Enter idle after tRC
H X X XX
Refreshing
NOP/BST
Nop Enter idle after tRC
L H H XX
READ/WRIT
Illegal
L H L XX
ACT/PRE/PALL
Illegal
L L H XX
REF/SELF/MRS
Illegal
L L L XX
Mode
DESL
Nop -> Enter idle after 2 Clocks
H X X XX
register
NOP
Nop -> Enter idle after 2 Clocks
L H H HX
setting
BST
Illegal
L H H LX
READ/WRIT
Illegal
L H L XX
ACT/PRE/PALL/
Illegal
L L X XX
REF/SELF/MRS
Notes:
1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode. All input buffers except CKE
will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address(BA), depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode. All input buffers except CKE
will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL .
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks in multi-bank devices.
14
Integrated Circuit Solution Inc.
DR037-0A 9/05/2003