IC42S16160 Datasheet, PDF (20/69 Pages) Integrated Circuit Solution Inc – 4M x 16Bit x 4 Banks (256-MBIT) SDRAM

IC42S16160
Precharge
The precharge command can be asserted anytime after tRAS(min.) is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters
the idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as
follows.
PrechargeE
CLK
Command
CAS latency = 2
DQ
Burst lengh=4
T0
T1
T2
T3
T4
T5
T6
T7
Read
PRE
Q0
Q1
Q2
Q3
Hi - Z
Command
CAS latency = 3
DQ
Read
PRE
Hi - Z
Q0
Q1
Q2
Q3
(t_RAS is satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL(min.)
specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be
calculated by dividing tDPL(min.) with the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
CAS latency
2
3
Read
-1
-2
Write
+ tDPL((min.)
+ tDPL((min.)
20
Integrated Circuit Solution Inc.
DR037-0A 9/05/2003