IC42S16160 Datasheet, PDF (50/69 Pages) Integrated Circuit Solution Inc – 4M x 16Bit x 4 Banks (256-MBIT) SDRAM

IC42S16160
Read and Write Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS
RAS
CAS
WE
*BS0
A10
ADD
RAa
RAa
CAa
CAb
CAc
DQM
Hi-Z
DQ
QAa0 QAa1 QAa2 QAa3
DAb0 DAb1
DAb3
QAc0 QAc1
QAc3
Activate Write
Command Command
Bank A Bank A
BS1=”L”, Bank C,D = Idle
50
Write
Command
Bank A
The Write Data
is Masked with a
Zero Clock
latency
Read
Command
Bank A
The Read Data
is Masked with
Two Clocks
Latency
Integrated Circuit Solution Inc.
DR037-0A 9/05/2003