IC42S32202L Datasheet, PDF (6/62 Pages) Integrated Circuit Solution Inc – 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM

IC42S32202/L
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth
table for the operation commands.
Table 2.Truth Table (Note (1),(2))
Command
State
BankActivate
Idle ⁽³⁾
BankPrecharge
Any
PrechargeAll
Any
Write
Active ⁽³⁾
Write and Auto Precharge Active ⁽³⁾
CKEn-1 CKE
H
X
H
X
H
X
H
X
H
X
DQM⁽⁶⁾ BS0,1
X
V
X
V
X
X
X
V
X
V
A10 A9-0
Row address
LX
HX
L Column
H ^address
(A0 ~A7)
CS# RAS# CAS# WE#
LL H H
LL H L
LL H L
LH L
L
LH L
L
Read
Active ⁽³⁾
H
XX
V
L _Column L H L
H
Read and Autoprecharge Active ⁽³⁾ H
XX
V
H
address
(A0 ~A7)
LH
L
H
Mode Register
Set Idle
H
XX
OP code
No-Operation
Any
H
XX
X
XX
Burst Stop
Active⁽⁴⁾
H
XX
X
XX
Device Deselect
Any
H
XX
X
XX
AutoRefresh
Idle
H
HX
X
XX
SelfRefresh Entry
Idle
H
L
X
X
XX
SelfRefresh Exit
Idle
L
HX
X
XX
(SelfRefresh)
Clock Suspend Mode Entry Active
H
L
X
X
XX
Power Down Mode Entry Any⁽⁵⁾
H
L
X
X
XX
Clock Suspend Mode Exit Active
L
HX
X
XX
Power Down Mode Exit Any
L
HX
X
XX
(PowerDown)
Data Write/Output Enable Active
H
XL
X
XX
Data Mask/Output Disable Active
H
XH
X
XX
LL
L
L
LH H H
LH H L
HX X X
LL
L
H
LL
L
H
HX X X
LH H H
XX X X
HX X X
LH H H
XX X X
HX X X
LH H H
XX X X
XX X X
Note:
1. V =Valid,X =Don ’t care,L =Logic low,H =Logic high
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1,2,4,8,and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle,device state is clock suspend mode.
6. DQM0-3
6
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004