IC42S32202L Datasheet, PDF (16/62 Pages) Integrated Circuit Solution Inc – 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM

IC42S32202/L
CLK
CKE
CS#
RAS#
CAS#
WE#
ADDR.
DQM
DQ ^Hi-Z
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCK2
Clock min.
Address Key
tRP
Precharge All
Mode Register _Any
Set Command _Command
Mode Register Set Cycle
The mode register is divided into various fields depending on functionality.
Address BS0,1 A10/AP A9 A8 A7 A6 A5 A4 A3
Function RFU* RFU* WBL Test Mode
CAS Latency
BT
*Note:RFU (Reserved for future use)should stay 0 during MRS cycle.
A2 A1 A0
Burst Length
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2,
4,8,or full page.
A2 A1
A0 Burst Length
00
0
1
00
1
2
01
0
4
01
1
8
10
0
Reserved
10
1
Reserved
11
0
Reserved
11
1
Full Page
16
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004