IC42S32202L Datasheet, PDF (52/62 Pages) Integrated Circuit Solution Inc – 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM

IC42S32202/L
Figure 18.2.Full Page Read Cycle (Burst Length=Full Page,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE ^High
CS#
RAS#
CAS#
WE#
BS0,1
RAx
RBx
RBy
A10
A0-A9
RAx
CAx
RBx
CBx
RBy
tRP
DQM
Hi-Z
DQ
Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx BBx+1 x+2 Bx+3 Bx+4 Bx+5 Bx+6
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does not
term in ate when the burst length is sat is fied;
the burst counter increments and continues
bursting beginning with the starting address.
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
52
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004