English
Language : 

IC42S32202L Datasheet, PDF (12/62 Pages) Integrated Circuit Solution Inc – 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
IC42S32202/L
CLK
T0
T1
T2
T3
T4
T5
T6
T7
T8
COMMAND
NOP
WRITEA
WRITEB
1 Clk Interval
NOP
NOP
NOP
NOP
NOP
NOP
DQ’s
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
Write Interrupted by a Write (Burst Length =4,CAS#Latency =2,3)
The Read command that interrupts a write burst without auto precharge function should be issued one cycle after
the clock edge in which the last data-in element is registered.In order to avoid data contention,input data must
be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the
following figure).Once the Read command is registered,the data inputs will be ignored and writes will not be
executed.
CLK
T0
T1
T2
T3
T4
T5
T6
T7
T8
COMMAND
NOP
WRITEA
READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=2
tCK2, DQ’s
DIN A0
don’t care
DOUT B0
DOUT B1
DOUT B2 DOUT B3
CAS# latency=3
tCK3 , DQ’s
DIN A0
don’t care
don’t care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Input data for the write is masked.
DI N
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
Write Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function
should be issued m cycles after the clock edge in which the last data-in element is registered,where m equals tWR/
tCK rounded up to the next whole number.In addition,the DQM signals must be used to mask input data,starting
with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/
PrechargeAll command is entered (refer to the following figure).
T0
T1
T2
T3
T4
T5
T6
CLK
DQM
COMMAND
WRITE
NOP
Precharge
NOP
tRP
NOP
Activate
NOP
ADDRESS
DQ
BANK
COL n
DIN
n
BANK (S)
t WR
n+1
ROW
: don t care
Note:The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
12
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004