IC42S32202L Datasheet, PDF (22/62 Pages) Integrated Circuit Solution Inc – 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM

IC42S32202/L
Electrical Characteristics and Recommended A.C.Operating Conditions
(VDD =3.3V ± 0.3V,Ta =0~70 C)(Note:5,6,7,8)
Symbol
A.C. Parameter
tRC
Row cycle time
(same bank)
tRRD
tRCD
tRP
Row activate to row activate delay
(different banks)
RAS# to CAS# delay
(same bank)
Precharge to refresh/row activate command
(same bank)
tRAS Row activate to precharge time
(same bank)
tCK2 Clock cycle time
CL* = 2
tCK3
CL* = 3
tAC2 Access time from CLK
CL* = 2
tAC3 (positive edge)
tOH
Data output hold time
CL* = 3
tCH
Clock high time
tCL
Clock low time
tIS
Data/Address/Control Input set-up time
tIH
Data/Address/Control Input hold time
tLZ
Data output low impedance
tHZ
tRDL
tCCD
tMRS
Data output high impedance
Last data in to row precharge
CAS# to CAS# Delay time
Mode Register Set cycle time
Min.
60/70/80
- 6/7/8
Max.
12/14/16
18/21/24
18/21/24
42/49/56
- / - /10
6/7/8
2/2.5/2.5
2/3/3
2/3/3
1.5/1.75/2
1
1
2
1
2
100,000
- / - /8
5.5/5.5/6
5.5/5.5/6
Unit Note
9
9
9
9
9
ns
9
9
10
10
10
10
9
8
CLK
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under “Absolute Maximum Ratings”may cause permanent damage to the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of
tCK and tRC.Input signals are changed one time during tCK.
4. These parameters depend on the output loading.Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
22
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004