IC42S32202L Datasheet, PDF (14/62 Pages) Integrated Circuit Solution Inc – 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM

IC42S32202/L
WRITE with Auto Precharge
· Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n
when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank n will begin after
t WR is met, where t WR begins when the READ to bank m is registered. The last valid WRITE to bank n will
be data-in registered one clock prior to the READ to bank m.
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
WRITE - AP
NOP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
Internal
States
BANK n
BANK m
Page Active
WRITE with Burst of 4
Page Active
Interrupt Burst, Write-Back
tWR _{- BANK n}
Precharge
tRP _{- BANKn}
READ with Burst of 4
NOP
tRP _{- BANKm}
ADDRESS
DQ
NOTE: 1. DQM is LOW.
BANK n,
COL a
DIN
a
DIN
a+1
BANK m,
COL d
CAS Latency = 3 (BANK m)
DOUT
d
DOUT
d+1
DON’T CARE
· Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank
n when registered. The PRECHARGE to bank n will begin after t WR is met, where t WR begins when the WRITE
to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE
to bank m.
WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
COMMAND
NOP
WRITE - AP
BANK n
NOP
Internal
States
BANK n
BANK m
Page Active
WRITE with Burst of 4
Page Active
ADDRESS
NOTE: 1. DQM is LOW.
BANK n,
COL a
DIN
a
DIN
a+1
DIN
a+2
WRITE - AP
BANK m
NOP
NOP
NOP
Interrupt Burst, Write-Back
tWR _{- BANK n}
WRITE with Burst of 4
Precharge
tRP - BANKn
t _{WR - BANK m}
Write-Back
BANK m,
COL d
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DON’T CARE
14
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004