IC42S32202L Datasheet, PDF (54/62 Pages) Integrated Circuit Solution Inc – 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM

IC42S32202/L
Figure 19.2.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE ^High
CS#
RAS#
CAS#
WE#
BS0,1
RAx
RBx
RBy
A10
A0-A9
RAx
CAx
RBx
CBx
RBy
DQM
Hi-Z
DQ
DAx DAx+1 _DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+55DBx+6
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Data is ignored
Precharge
Command
Bank B
The burst counter wraps Full Page burst operation does
from the highest order
not terminate when the burst
page address back to zero length is satisfied; the burst counter
during this time interval increments and continues bursting
beginning with the starting address.
Burst Stop
Command
Activate
Command
Bank B
54
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004