IC42S32202L Datasheet, PDF (13/62 Pages) Integrated Circuit Solution Inc – 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM

IC42S32202/L
6 Concurrent Auto Precharge
An access command (READ or WRITE) to another bank while an access command with auto precharge enabled
is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE.
ICSI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.
READ with Auto Precharge
· Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n,
CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is regis-tered.
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
READ - AP
BANK n
NOP
READ - AP
BANK m
NOP
NOP
Internal
States
BANK n
BANK m
Page Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
tRP _{- BANK n}
READ with Burst of 4
NOP
NOP
Idle
tRP _{- BANKm}
Precharge
ADDRESS
BANK n,
COL a
BANK m,
COL d
DQ
DOUT
a
DOUT
a+1
DOUT
d
DOUT
d+1
CAS Latency = 3 (BANK n)
NOTE: DQM is LOW.
CAS Latency = 3 (BANK m)
DON T CARE
· Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered.
READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ - AP
BANK n
NOP
NOP
Internal
States
BANK n
Page
Active
READ with Burst of 4
BANK m
Page Active
NOP
WRITE - AP
NOP
BANK m
NOP
Interrupt Burst, Precharge
tRP _{-BANK n}
WRITE with Burst of 4
NOP
Idle
t _{WR - BANK m}
Write-Back
ADDRESS
1
DQM
BANK n,
COL a
BANK m,
COL d
DQ
DOUT
DIN
a
d
DIN
d+1
CAS Latency = 3 (BANK n)
NOTE: 1. DQM is HIGH at T2 to prevent D OUT-a+1 from contending with D IN-d at T4.
DIN
d+2
DIN
d+3
DON’T CARE
Integrated Circuit Solution Inc.
13
DR042-0C 08/17/2004