IC42S32202L Datasheet, PDF (55/62 Pages) Integrated Circuit Solution Inc – 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM

IC42S32202/L
Figure 19.3.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE _High
CS#
RAS#
CAS#
WE#
BS0,1
A10
RAx
A0-A9
RAx
DQM
Hi-Z
DQ
Activate
Command
Bank A
RBx
RBy
CAx
RBx
CBx
RBy
DAx DAx+1 _DAx+2 DAx+3 _DAx-1 DAx DAx+1 DBx DBx+1
DBx+3 DBx+4 DBx+5
Data is ignored
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
Integrated Circuit Solution Inc.
55
DR042-0C 08/17/2004