IC-MD Datasheet, PDF (7/23 Pages) IC-Haus GmbH – ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

iC-MD RS-422 QUADRATURE
preliminary
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
CONFIGURATION PARAMETERS
Rev A1, Page 7/23
Read/Write Registers
Read-Only Registers
Configuration
INVZ(1:0)
invert Z signal
EXCH(2:0) exchange inputs AB
CNTCFG(2:0) counter configuration
TTL
TTL/differential inputs
CBZ(1:0)
clear counter by zero
CFGZ(1:0) zero signal configuration
TPCFG(1:0) TPI configuration
PRIOR
SPI/BiSS communication priority
MASK(9:0) error/warning mask
NMASK(1:0) error/warning not mask
LVDS
LVDS/RS-422 differential inputs
CH2SEL
BiSS channel 2 select
ENCH2
BiSS channel 2 enable
CH1SEL
BiSS channel 1 select
ENCH1
BiSS channel 1 enable
CH0SEL
BiSS channel 0 select
NENCH0
BiSS channel 0 not enable
Table 5: Register description
Write-Only Registers
Instructions
ACT1 set value of ACT1 pin
ACT0 set value of ACT0 pin
TP
latch TP1 and TP2
ZCEN enable zero codification
ABRES2 reset AB counter 2
ABRES1 reset AB counter 1
ABRES0 reset AB counter 0
Table 6: Instruction Byte
Status
AB
counter values
NERR error bit (low active)
NWARN warning bit (low active)
TP1
touch-probe 1 register
NTPVAL touch-probe valid (low active)
NABERR AB counter error (low active)
TP2
touch-probe 2 register
REF
reference register
UPD
update register
NUPDVAL update register valid (low active)
Table 7: Counter Registers
Error
ABERRx AB signals error in counter x
EXTERR external error
Table 8: Error Registers
Warning
OVFx
overflow in counter x
ZEROx signals zero value in counter x
PDWN
power-down reset
RVAL
REF value valid
UPDVAL update register up to date
OVFREF overflow in REF counter
TPVAL
new touch-probe value available
EXTWARN external warning
COMCOL communication collision
TPS
actual TPI pin status
ENSSI
SSI enabled
Table 9: Warning Registers