IC-MD Datasheet, PDF (11/23 Pages) IC-Haus GmbH – ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

iC-MD RS-422 QUADRATURE
preliminary
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
48 BIT COUNTER
Rev A1, Page 11/23
iC-MD has a 48 bit counter configurable as from one
up to three counters with bit lengths from 16 to 48 bit.
Table 16 shows all the possible counters configuration.
The counter configuration is given by the registers
CNTCFG as shown in table 16. If it is configured with
more than one counter, the input stage must be set to
TTL (table 12).
CNTCFG
Addr. 0x00; bit (2:0)
000
Code
Counter Configuration
000
1x24 bit counter
001
2x24 bit counter
010
1x48 bit counter
100
1x32 bit counter
101
1x32 bit + 1x16 bit counter
011
1x16 bit counter
110
2x16 bit counter
111
3x16 bit counter
Table 16: Counter Length
The 48 bit register of the AB counter is also used as
"SPI data channel" for data exchanging between SPI
and BiSS interface, for that purpose the bit CH0SEL
(table 45) must be set to 1. When CH0SEL = 1, the
counting function for all the counters is deactivated.
Index Signal (Z)
In default operation configuration, the index signal (Z)
is active when A = B = 1, as shown in table 17 with
EXCH = 0 and INVZ = 0. All other configurations are
also possible.
CFGZ
Addr. 0x01; bit (4:3)
00
Code
Function:
00
Z active: when A = 1 B = 1
01
Z active: when A = 1 B = 0
10
Z active: when A = 0 B = 1
11
Z active: when A = 0 B = 0
Table 17: Index Signal Configuration
It can also be deactivated the clearing of counter by
the index signal with the configuration bit CBZ ( table
18 ).
The CBZ configuration is only applicable after the sec-
ond index pulse after power-on or the activation of
ZCEN (table 23), because after it, the iC-MD will reset
the counter value by the firsts two index pulse, inde-
pendently of the CBZ configuration, in order to have
the AB Counter value referenced to the second index
pulse. By default, CBZ is set to 0, also the counters
are not reset to 0 by the index signal. But the firsts two
Index pulse always reset the counters.
CBZ
Addr. 0x01; bit (6:5)
00
Code
Function
x1
CNT0 cleared by Z0 signal
1x
CNT1 cleared by Z1 signal
Table 18: Clear by Z