IC-MD Datasheet, PDF (2/23 Pages) IC-Haus GmbH – ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

iC-MD RS-422 QUADRATURE
preliminary
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
Rev A1, Page 2/23
DESCRIPTION
iC-MD evaluates incremental encoder signals with A,
B and index tracks from up to three encoders.
After power-on the iC-MD has all the RAM bits at 0 as
default configuration, that means one 24 bit counter
configured, and differential inputs. The device can be
programmed via the SPI interface or BiSS Interface.
The 48 bit counter can be configured as up to three
counters with variable counter depths of 16, 24, 32 or
48 bits, but the sum of bits of all the configured coun-
ters can not be higher than 48 bits. Some of the pos-
sible configurations are 1x48 bit, 2x24 bit, 3x16 bit,
1x32 + 1x16 bit. Each edge of the synchronized en-
coder signal counts (fourfold edge evaluation).
An additional 24bit counter REF counter is used to
store the distance (number of pulses) between the
first two index pulses after power-on and the distance
between every last two index pulses in UPD register.
An event at the input pin TPI (configurable as rising,
falling or both edges) loads the register TP1 with the
actual value of the counter 0, and shift the old value
of TP1 in register TP2. This registers can also be
loads through the instruction bit TP, via SPI or BiSS
(Register communication).
Two bidirectional ports are used as error and warning
output (low active) and can be pulled down from out-
side to signals an external error or external warning.
This external error and warning are internally latched
in the status registers.
A set of status registers monitor the status of the
counter, TP1, TP2, REF, UPD, power on and external
error and warning pins.
The BiSS Interface reads out the counter and regis-
ters TP1, TP2 and UPD as Sensor data. REF regis-
ter is read via BiSS register communication.
PACKAGES
PIN CONFIGURATION
TSSOP20 4.4 mm, lead pitch 0.65 mm
1
SLO
2
SLI
3
MA
4
AP
5
AN
6
BP
7
BN
8
CP
9
CN
10
GND
20
TPI
19
ACT1
18
ACT0
17
VDD
16
NCS
15
SCK
14
MOSI
13
MISO
12
nWARN
11
nERR
PIN FUNCTIONS
No. Name Function
1 SLO BiSS/SSI Interface, data output
2 SLI
BiSS/SSI Interface, data input
3 MA
BiSS/SSI Interface, clock input
4 AP
Signal Input (CNT0 / CNT0)
5 AN
Signal Input (CNT0 / CNT0)
6 BP
Signal Input (CNT0 / CNT1)
7 BN
Signal Input (CNT1 / CNT1)
8 CP
Signal Input (CNT1 / CNT2)
9 CN
Signal Input (CNT1 / CNT2)
10 GND Ground
11 NERR Error Message Output (low active)
/ System Error Message Input
12 NWARN Warning Message Output (low active)
/ System Warning Message Input
13 MISO SPI Interface, data ouput
14 MOSI SPI Interface, data input
15 SCK SPI Interface, clock input
16 NCS SPI Interface, chip select (low active)
17 VDD 3.0 . . . 5.5 VSupply Voltage
18 ACT0 Actuator Output 0
19 ACT1 Actuator Output 1
20 TPI
Touch Probe Input