IC-MD Datasheet, PDF (20/23 Pages) IC-Haus GmbH – ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

iC-MD RS-422 QUADRATURE
preliminary
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
BiSS and SSI INTERFACE
Rev A1, Page 20/23
The BiSS interface is a bidirectional serial interface,
which is used to read out the sensor data values and
to write and read the internal configuration registers.
For a detailed description of the protocol, see the BiSS
C specification.
It consist of 3 configurable channels:
channel
CH0
CH1
CH2
Notes
eata
AB counter
SPI Channel
UPD
TP1
TP1
TP2
error
warning data length CRC polynom
NERR NWARN 16 + 2 bit 1000011
24 + 2 bit
32 + 2 bit
48 + 2 bit
NERR NSPICHVAL 16 + 2 bit 1000011
24 + 2 bit
32 + 2 bit
48 + 2 bit
NABERR NUPDVAL 24 + 2 bit
100101
NABERR NTPVAL 24 + 2 bit
100101
NABERR NTPVAL 24 + 2 bit
100101
NABERR NTPVAL 24 + 2 bit
100101
channel 0 data length configurable via:
CNTCFG (Adr.0x00, bit 3:0)
CRC mode
inverted
inverted
inverted
inverted
inverted
inverted
Table 44: BiSS Channels
The error (NERR) and warning (NWARN) bit of the
channel 0 signal the same data to be output at the pins
NERR and NWARN, it’s by default:
The three channel are enabled by default, but all of
them can be disable with the registers NENCH0 (table
46) and ENCHx (table 47)
NERR: ABERR (AB signal error)
NENCH0
Addr. 0x04; bit (2)
0
Code
Function
NWARN: UPDVAL (UPD Reg. up to date)
0
BiSS channel 0 enabled
1
BiSS channel 0 disabled
This bits can also be configured like the NERR and
NWARN outputs, with the registers MASK (table 40)
and NMASK(table 41)
Two different data can be selected for each chan-
nel, register CHxSEL (table 45) selects the data to be
transmitted by the channels.
CHxSEL
Addr. 0x04; bit (7,5,3)
000
Code
Function
XX0
channel 0: AB counter data
XX1
channel 0: SPI data channel
X0X
channel 1: UPD data
X1X
channel 1: TP1 data
0XX
channel 2: TP1 data
1XX
channel 2: TP2 data
Table 45: BiSS Channel Selection
Table 46: Not Enable BiSS Channel 0
ENCHx
Addr. 0x04; bit (6,4)
00
Code
Function
X0
BiSS channel 1 disabled
0X
BiSS channel 2 disabled
Table 47: Enable BiSS Channel 1 and 2
SSI Protocol
An SSI protocol is selected if the input pin SLI is open.
This enable signal has an internal digital filter of 5 µs.
A clock pulse train from a controller is used to gate out
sensor data. Between each clock pulse train there is a
SSI timeout during which fresh data is moved into the
register. Data is shifted out when the iC-MD receives
a pulse train from the controller. When the least sig-