IC-MD Datasheet, PDF (18/23 Pages) IC-Haus GmbH – ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

iC-MD RS-422 QUADRATURE
preliminary
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
SPI INTERFACE
Rev A1, Page 18/23
The Serial Peripheral Interface (SPI) of iC-MD consists
of a SPI slave interface with polarity 0 and phase 0.
• The rising edge of NCS ends all data transfer and
resets internal counter and command register
Each transmission starts with a falling edge of NCS
and ends with the rising edge. During transmission,
commands and data are controlled by SCK and NCS
according to the following rules:
• Data transfer out from MISO starts with the falling
edge of SCK immediately after the last bit of the
SPI command is sampled in on the rising edge
of SCK
• Commands and data are shifted; MSB first, LSB
last
• Each output data/status bits are shifted out on
the falling edge of SCK (MISO line) and each bit
is sampled on the rising edge of SCK (Polarity 0,
Phase 0).
• After the device is selected with the falling edge
of NCS, an 8-bit command is received. The com-
mand defines the operations to be performed
(Write/Read) and the address.
• Data transfer to MOSI continues immediately af-
ter receiving the command in all cases where
data is to be written to iC-MD internal registers
SPI Communication
The first byte to be transmitted to the iC-MD via SPI is
the instruction (or command) wich determine the com-
munication direction (read or write), and has the follow-
ing structure:
Bit 7
R/W
Bit 6
Bit 5
SPI Commands
Bit 4
Bit 3
Bit 2
ADDRESS(6:0)
Table 42: SPI command structure
Bit 1
Bit 0
The following diagrams show the SPI write and read
processes.
NCS
SCLK
MOSI
MISO
0
ADR(6:0)
Polarity 0, Phase 0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
X
Byte to write in ADR
Byte to write in ADR+1
High Impedance
Figure 6: SPI Write Data
NCS
SCLK
MOSI
MISO
1
ADDRESS(6:0)
High Impedance
Polarity 0, Phase 0
n
n-1
n-2
n-3
n-4
n-5
don't care
5
4
3
2
1
0
X High Impedance
Figure 7: SPI Read Data
The data length to be written is always 8 bit, but it is if the NCS signal is not reset and SCLK continues be-
possible to transmit several bytes of data consecutively ing clocked. The address transmitted is then the start