IC-MD Datasheet, PDF (15/23 Pages) IC-Haus GmbH – ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

iC-MD RS-422 QUADRATURE
preliminary
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
COMMUNICATION CONTROL
Rev A1, Page 15/23
iC-MD can communicate simultaneously via SPI and ^ABRES2
Addr. 0x30; bit 2
0
BiSS in order to exchange data between SPI and BiSS. ^Code
Function
For this purpose, SPI writes the data to be read by 1
reset of counter 2
BiSS in the AB register, and BiSS reads the SPICH
(BiSS channel 0 configured as SPICH, see table 45).
Table 22: Counter 2 Reset
If both interfaces attempt to read or write at the same
time a different RAM address than the SPICH (Adr.
0x20 to 0x25), then the bit error COMCOL (table 37)
is set and the communication of the interface without
priority (see table 43) is not valid.
Instruction Byte
Register address 0x30 contains the write only instruc-
tion byte. When one of these bits is set to 1, then the
corresponding operation is executed and then set back
to 0, excepts the bits ACT0 and ACT1 which remain to
the written value.
ZCEN
Addr. 0x30; bit 3
1
Code
Function
1
enable zero codification
Table 23: Enable Zero Codification
TP
Code
1
Notes
Addr. 0x30; bit 4
-
Function
load TP2 with TP1 value, and TP1 with ABCNT
value
counter must be configured to 24 bit length
Table 24: Touch Probe Instruction
The instruction bits ACT0 and ACT1 set the actuator
pins ACT0 and ACT1 to high or low voltage.
ACT0
Addr. 0x30; bit 5
0
ABRES0
Addr. 0x30; bit 0
0
Code
Function
Code
Function
0
actuator pin 0 set to GND
1
reset of counter 0
1
actuator pin 0 set to VDD
Table 20: Counter 0 Reset
Table 25: Actuator Pin 0
ACT1
Addr. 0x30; bit 6
0
ABRES1
Addr. 0x30; bit 1
0
Code
Function
Code
Function
0
actuator pin 1 set to GND
1
reset of counter 1
1
actuator pin 1 set to VDD
Table 21: Counter 1 Reset
Table 26: Actuator Pin 1
STATUS REGISTER and ERROR/WARNING INDICATION
The three bytes status registers (Adr. 0x48 to 0x4A)
indicate the state of the iC-MD. All the status bits are
latched (except TPS) when an error/warning occurs
and are reset when reading the error/warning via SPI
or BiSS excepts RVAL. The status bits TPVAL and UP-
DVAL are also reset by reading the register TP1 and
UPD respectively.
Two of this status bits are error bits; ABERR (AB de-
codification error, table 27) and EXTERR (external er-
ror, table 35), all others status bits signal warnings.
The status bit TPS (table 38) is not latched, it signals
the actual state of the input pin TPI.
Status bits ABERRx indicate a decodification error of
the AB inputs, it ocurrs if the counting frequency is too
high or if two incremental edges are too close (PHab2,
Spec. Item No.303).