IC-MD Datasheet, PDF(19/23 Page) IC-Haus GmbH – ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

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IC-MD Datasheet, PDF (19/23 Pages) IC-Haus GmbH – ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

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iC-MD RS-422 QUADRATURE

preliminary

ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

Rev A1, Page 19/23

address which is internally increased by 1 following

each transmitted byte.

The data length to be read after the read instruction is

variable:

8 bit

For conï¬guration data (Adr.- 0x00 to 0x07), REF and

SPICH (Adr.- 0x10 to 0x25), ROM (Adr.- 0x42, 0x43)

and Status Bit (Adr.- 0x48 to 0x4A). But it is possi-

ble to read several bytes of data consecutively if the

NCS signal is not reset and SCLK continues being

clocked. The address transmitted is then the start ad-

dress which is internally increased by 1 following each

transmitted byte.

24+2 bit

For TP1, TP2 and UPD registers.

Variable

For counter data, it depends on the counter conï¬gura-

tion CNTCFG (Adr. 0x00 bit (2:0)). See the table 16.

The total length is CNT length + 2 bit (NERR, NWARN)

Interface Priority

The Conï¬guration bit PRIOR (Adr. 0x03, bit 1), set

which interface has priority when taking place a Read-

/Write interface collision. It means that if BiSS and SPI

try to access to the conï¬guration register at the same

time, then only the one with the priority will write/read

succefully the register. The error in the interface with-

out priority will be signalized by the collision Status bit:

SPICOL or BISSCOL, Adr.0x4A, bit(1:0).

PRIOR

Addr. 0x03; bit 1

Code

Function

BiSS priority

SPI priority

Table 43: Interface Priority

SPI Channel: SPI to BiSS communication

The counter register is also used for the transmission

of data from SPI to BiSS. The data exchanging take

place as following:

1. SPI writes the data to be transmitted in address

0x20 to 0x25, this data is written in the counter

registers. The data lenght to be transmitted is

selected by CNTCFG (Table 16) and can be con-

ï¬gured as 16, 24, 32 or 48-bit

2. After the writing process, the bit SPICHVAL is set

to 1 and read via BiSS as Warning bit of channel

3. BiSS reads out the channel 0, the data written

via SPI and two status bits, NERR and NWARN

wich indicates if the read data is valid.

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