IC-MD Datasheet, PDF (16/23 Pages) IC-Haus GmbH – ENCODER RECEIVER/COUNTER WITH SPI AND BiSS

iC-MD RS-422 QUADRATURE
preliminary
ENCODER RECEIVER/COUNTER WITH SPI AND BiSS
Rev A1, Page 16/23
ABERRx
Code
0
1
Notes
Addr. 0x48, 0x49, 0x4A;
bit 7
Description
No decodification error in counter x
Decodification error in counter x
x = 0, 1, 2
Reset by reading Adr. 0x48 (ABERR0), 0x49
(ABERR1) and 0x4A (ABERR2)
The corresponding counter must be reset (ABRES)
after an error
Table 27: AB Decodification Error
The maximum counting range of the counters depends
on the counter configuration (see table 16). A counter
with the bit length "n" has the maximum counting range
will be from -2^n-1 up to 2^n-1-1. The corresponding bit
OVFx is set to 1 if the counter exceeds these values.
RVAL status bit indicates that the reference value was
load in the REF register, after the "Zero Codification"
process. After power-on, this bit remains at 0 until the
second different Index pulse.
RVAL
Code
0
1
Notes
Addr. 0x48; bit 3
Description
REF Reg. not valid
REF Reg. valid
Reset by the instruction ZCEN(see table 23)
Table 31: REF Register Valid
Every time that the UPD register is loaded, the status
bit UPDVAL (UPD valid) is set to 1 until the status bit
UPD or the register UPD is read via SPI or BiSS.
OVFx
Code
0
1
Notes
Addr. 0x48, 0x49, 0x4A;
bit 6
Description
no overflow in counter x
overflow in counter x
x = 0, 1, 2
reset by reading Adr. 0x48 (OVF0), 0x49 (OVF1)
and 0x4A (OVF2)
UPDVAL
Code
0
1
Notes
Addr. 0x48; bit 2
Description
UPD Reg. not valid
UPD Reg. valid
Reset by reading Adr. 0x48 or the register UPD via
SPI (Adr. 0x0A) or BiSS (Channel 1)
Table 32: UPD Register Valid
Table 28: Counter Overflow Warning
ZEROx bits indicate that the counter value has
reached the zero value.
ZEROx
Code
0
1
Notes
Addr. 0x48, 0x49, 0x4A;
bit 5
Description
no zero of counter x
zero of counter x
x = 0, 1, 2
reset by reading Adr. 0x48 (ZERO0), 0x49
(ZERO1) and 0x4A (ZERO2)
Table 29: Zero Value in Counter x
If VDD reaches the power off supply level (VDDoff,
Spec. Item No. 602), the iC-MD is reset and the RAM
initialized to the default value. Status bit PDWN indi-
cates that this initialization has taken place.
PDWN
Code
0
1
Notes
Addr. 0x48, 0x49, 0x4A;
bit 4
Description
No undervoltage
Undervoltage
Reset by reading Adr. 0x48, 0x49 or 0x4A
If the number of AB edges between two index signals
is greater than 2²³-1=8388607 or lower than -2²³=-
8388608 the status bit OVFREF is set to 1 and indi-
cates that the value of the UPD and REF registers are
not valid.
OVFREF
Code
0
1
Notes
Addr. 0x48; bit 1
Description
No Overflow in reference counter
Overflow in reference counter
Reset by reading Adr. 0x48
Table 33: Reference Counter Overflow
After loading TP1/TP2 register, either via pin TPI or in-
struction TP (see table 24), the bit TPVAL is set to 1
and remains at 1 until the reading of TPVAL, TP1 or
TP2 via SPI or BiSS.
TPVAL
Code
0
1
Notes
Addr. 0x48; bit 0
Description
TPx registers not loaded
New value loaded in TPx
Reset by reading Adr. 0x48, register TP1 or register
TP2 via SPI (Adr. 0x0C and 0x0E) or BiSS
(channel 1 and channel 2, see table 45)
Table 30: Undervoltage Reset
Table 34: Touch-Probe Valid