IC-GD Datasheet, PDF (53/55 Pages) IC-Haus GmbH – UNIVERSAL I/O INTERFACE

iC-GD
UNIVERSAL I/O INTERFACE
preliminary
Rev A1, Page 53/55
DIAG_SEL_CH
DIAG_SEL_CH
/
0000
VB
0001
VNB
0010
VCC
0011
VDA
0100
VPA
0101
VPD
0110
VI
0111
V020
1000
V420
1001
Channel 1: Digital output current
1010
Channel 2: Digital output current
RW - 0000
Table 91: Diagnostics selection
DIAG_CH
/
R-/
see Tab. 12
Table 92: Diagnostics channel
WR_EEPROM_CONF
Register WR_EEPROM_CONF stores the current con-
figuration. After writing 0x96 to this register, the chip
automatically writes the current configuration, i.e. all
registers marked with ’K’, to the EEPROM. Subse-
quently, also the valid CRC checksum is written. When
the writing process is completed, the register is set;
0 signifies error-free writing, 1 signifies an error. This
register can be polled for the end of the writing process.
WR_EEPROM_CONF
L-/
0x96 write
Starts write
0x96 read
Write in progress
0x00 read
Last write succesfull
0x01 read
Last write failed
RW - 0x00
Table 93: Write configuration
In all cases, the chip operates as an I²C master at up
to 100 kbit/s. The interface is not capable of multi-mas-
ter operation. The 7-bit addressing mode is supported.
Note that an EEPROM with a page size of at least 2
bytes is required for operation. When writing several
bytes to EEPROM it must be additionally ensured that
the page limit is not exceeded. More information can
be found in the relevant datasheet.
The following registers are of importance to use the
bridge:
• I2C_DEV_ADR: This register contains the address of
the chips to be addressed, e.g. 0xA0 for EEPROMs
• I2C_PTR: This register operates as pointer. It ad-
dresses a particular register at the addressed chip.
• I2C_MODE: According to table 96, it can be selected
between the modes RD; RD[PTR], and WR[PTR].
• I2C_BYTES: This register indicates the number of
bytes that are to be read or written. Values between
1 and 4 are valid.
• I2C_DATA_Bx: During the writing process, the bytes
stored here are written; during read process the bytes
that are read are stored here.
Except for the data bytes, no I²C register is changed
during I²C communication. A valid setting can be main-
tained for an infinite time. If the registers are set cor-
rectly, the communication can be started via opcode
I²C-TRANSFER. Opcode I²C Status can be polled for
its end. Note that after successful writing accesses,
EEPROMs require time for the internal writing. Within
this time-window it does not respond to requests. When
writing, a waiting period in accordance with the EEP-
ROM specification is to be maintained.
I2C_DEV_ADR
/
Chip address
RW - undef
Table 94: I²C device address
I²C
The chip contains an I²C interface. An external EEP-
ROM must be connected to it which contains the con-
figuration and calibration data required for operation.
Additionally, it enables accessing other chips in the form
of a bridge between SPI and I²C. For example temper-
ature sensors with I²C interface can be controlled and
their temperature data can be written via SPI on the
registers of the cold junction compensation.
The currently valid configuration data can be trans-
mitted automatically to the EEPROM via register
WR_EEPROM_CONF. The calibration data must be
written to the EEPROM in bridge mode and the match-
ing checksums must be transmitted.
I2C_PTR
/
Pointer to address the chip
Table 95: I²C pointer
I2C_MODE
/
0x1
RD: Read from current address
0x2
RD[PTR]: Write from [PTR]
0x4
WR[PTR]: Read from [PTR]
Table 96: I²C mode
I2C_DATA_Bx
/
Data bytes for I²C communikation
Table 97: I²C data bytes
RW - undef
RW - undef
RW - undef