IC-GD Datasheet, PDF (40/55 Pages) IC-Haus GmbH – UNIVERSAL I/O INTERFACE

iC-GD
UNIVERSAL I/O INTERFACE
OPCODE-BASED DATA
preliminary
Rev A1, Page 40/55
PROCESS_DATA_x
The register PROCESS_DATA_x is controlled via the
opcode and therefore does not contain a register ad-
dress itself.
PROCESS_DATA_x (TM)
P
R-/
bit 15:0
Temperature, see Tab. 10
Table 29: Process data primary channel in TM mode
The meaning and length of the opcode complies with
the selected mode of the IO_SEL_x register and other
involved registers if applicable. The register can trans-
mit 32-bit, 16-bit, and 8-bit data and optionally can be
switched off entirely. It contains the data of the primary
channels.
CH_STAT_REG
The register CH_STAT_REG is controlled directly via
the opcode and therefore does not contain a register
address.
PROCESS_DATA_x (DI)
P
R-/
bit 6:0
0000000
bit 7
Digital input after spike filter, optionally inverted
Table 24: Process data primary channel in DI mode
The states of both primary channels and other sta-
tus bits are stored in this register. The states of the
channels depend on the selected mode (IO_SEL_xP)
and can be activated via the EN_CH_STAT_xP register.
When reading, the bits are reset automatically.
PROCESS_DATA_x (DO/PWM) P
RW - 0x00
bit 6:0
0000000
bit 7 OUT Output, depending on DO_SEL, optionally inverted:
PUSH-PULL: Output bit
LOW-SIDE: 0 = line low (driver active)
HIGH-SIDE: 1 = line high (driver active)
bit 7 IN(*) Reading of the physical line: digital input after spike
filter, optionally inverted
Table 25: Process data primary channel in DO mode
(*) No overlapping since there are different byes when
writing and reading back.
PROCESS_DATA_x (VI/CI)
P
R-/
bit 15:0
Analog input value, see Tab. 5
Table 26: Process data primary channel in VI/CI mode
Note that bit 2, 3, 4, 5, and 6 can only be (de-)activated
together because they are controlled by the same bit
of the EN_CH_STAT_xP register. They assume their
status independently though. In the following tables this
is marked by horizontal lines.
Figure 7 explains the connection between the regis-
ters CH_STAT, SPV_REG, IRQ_FLAG_REG, and their
enable registers.
CH_STAT_REG
P+
R+RST - 0x0000
bit 6:0
CH_STAT_1P, see Table 31 to 37
bit 7
CH_STAT_12S_SUM – Sum of CH_STAT_1S and
CH_STAT_2S
bit 14:8
CH_STAT_2P, see Table 31 to 37
bit 15
SPV_REG_SUM – Sum of SPV_REG
PROCESS_DATA_x (VO/CO)
P
bit 1:0
Unused
bit 15:2
Analog output value, see Tab. 7
W - 0x0000
Table 27: Process data primary channel in VO/CO
mode
PROCESS_DATA_x (CNT)
P
bit 31:0
Counter value (1 LSB = 125 ns)
R(*) - 0x0000
0000
Table 30: Channel status register
CH_STAT_x (DI)
P
R+RST -
0000000
bit 0
Mapping of digital input to spike filter and optional
invertion (*)
bit 6
1 = Overcurrent UNx
Table 31: CH_STAT_x in DI mode
Table 28: Process data primary channel in CNT mode
(*) When bit ENDOSC_x is activated, the output of the
(*) Setting of the counter possible via register communi- comparator that is also available for SPI is mapped
cation.
instead.