IC-GD Datasheet, PDF (49/55 Pages) IC-Haus GmbH – UNIVERSAL I/O INTERFACE

iC-GD
UNIVERSAL I/O INTERFACE
preliminary
Rev A1, Page 49/55
DIG_FIL_x
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
LK-PS
RW - 0x0
valid for FIL_HB_x = ’0’
2 kHz
1 kHz
500 Hz
250 Hz
125 Hz
62.5 Hz
31.2 Hz
15.6 Hz
7.8 Hz
3.9 Hz
1.9 Hz
0.97 Hz
0.50 Hz
valid for FIL_HB_x = ’1’
3.50 kHz (only with voltage measurement)
1.75 kHz (only with voltage measurement)
875 Hz
440 Hz
220 Hz
110 Hz
55 Hz
27.5 Hz
14 Hz
7 Hz
3.5 Hz
1.75 Hz
0.875 Hz
Table 67: Digitale filter cut-off frequencies (rounded)
FIL_HB_x
Via register FIL_HB_x, the digital input filter for the ana-
log signals can be switched into a faster mode with
reduced latency but flatter amplitude response. This
involves an internal deactivation of the half-band filters.
See register ’DIG_FIL_x’.
FIL_HB
0
1
LK-PS
RW - 0
Steeper amplitude response with higher latency
Flatter amplitude response with lower latency
Table 68: FIL_HB_x
FIL_ITP
0
1
LK-PS
Active interpolation with higher latency
Deactive interpolation with lower latency
RW - 0
Table 69: FIL_ITP_x
SPIKE_FIL_x
The digital spike filter can be set for every channel sep-
arately. It serves to filter the digital input for spurious
pulses up to a configurable length.
The digital spike filter can be set via the 4-bit-wide regis-
ter SPIKE_FIL_x in the range of 0 up to approx. 262 ms.
To deactivate the filter, the time can be set to 0. Inter-
nally, the filter operates with an 8-bit counter. If the input
is 0, the counter is counted down, if it is 1, it is counted
up. If the counter reaches 0, the output is set to 0. If
the counter achieves its maximum value dependent on
the filter width, it is set to 1.
Table 70 summarizes the settings of SPIKE_FIL_x, the
resulting filter time and in brackets the internal sample
rate and filter width. The given times have an accuracy
of ±1 clock. This is equal to an accuracy e.g. at 8 MHz
sampling of ±125 ns.
SPIKE_FIL_x
LK-PS
RW - 0x7
0x0
0 µs . . . . . . . . . . . . . . . . . . . . . . . . . (8 MHz, spike-filter off)
0x1
16 µs . . . . . . . . . . . . . . . . . . . . . . . . (8 MHz, 7-bit counter)
0x2
32 µs . . . . . . . . . . . . . . . . . . . . . . . . (8 MHz, 8-bit counter)
0x3
64 µs . . . . . . . . . . . . . . . . . . . . . . . . (4 MHz, 8-bit counter)
0x4
128 µs . . . . . . . . . . . . . . . . . . . . . . . (2 MHz, 8-bit counter)
0x5
256 µs . . . . . . . . . . . . . . . . . . . . . . . (1 MHz, 8-bit counter)
0x6
512 µs . . . . . . . . . . . . . . . . . . . . . (500 kHz, 8-bit counter)
0x7
1.024 ms . . . . . . . . . . . . . . . . . . . (250 kHz, 8-bit counter)
0x8
2.048 ms . . . . . . . . . . . . . . . . . . . (125 kHz, 8-bit counter)
0x9
4.096 ms . . . . . . . . . . . . . . . . . . (62.5 kHz, 8-bit counter)
0xA
8.192 ms . . . . . . . . . . . . . . . . . (31.25 kHz, 8-bit counter)
0xB
16.38 ms . . . . . . . . . . . . . . . . . (15.63 kHz, 8-bit counter)
0xC
32.77 ms . . . . . . . . . . . . . . . . . (7.813 kHz, 8-bit counter)
0xD
65.54 ms . . . . . . . . . . . . . . . . . (3.906 kHz, 8-bit counter)
0xE
131.1 ms . . . . . . . . . . . . . . . . . (1.953 kHz, 8-bit counter)
0xF
262.1 ms . . . . . . . . . . . . . . . . . (0.977 kHz, 8-bit counter)
Table 70: Spike-filtertime setting
FIL_ITP_x
Via register FIL_ITP_x, the digital input filter for the
analog signals can be switched into a faster mode with
reduced latency but much lower sample rate. This in-
volves a deactivation of the interpolation which results
in about halving the latency.
AI_LOWER_x, AI_UPPER_x
Registers AI_LOWER_x and AI_UPPER_x describe
the valid range in which the analog input should stay. If
the detection in the EN_CH_STAT_xX register is acti-
vated, a status bit indicates when this range is left. The
status bit remains set until the status register is read to
ensure that temporarily leaving the range will also be
detected.