IC-GD Datasheet, PDF (26/55 Pages) IC-Haus GmbH – UNIVERSAL I/O INTERFACE

iC-GD
UNIVERSAL I/O INTERFACE
CALIBRATION
preliminary
Rev A1, Page 26/55
Bandgap
The adjustable on-chip, second-order temperature-com-
pensated bandgap is the voltage reference of the iC-GD.
For adjusting the voltage reference, the parameter with
the lowest temperature coefficient is calculated. This
value is calculated during the production process and
stored on-chip (OTP). It can be overwritten by a value
stored in the external EEPROM. A bandgap voltage
voltage that is too low is indicated in the supervisory
register SPV_INT.
Bias
The reference current of the iC-GD is generated by
an external resistor, RREF, between the pins RP and
RN. To achieve a high accuracy of the current out-
puts, a resistor with a low temperature coefficient is
required. The absolute value is not critical, but must
not exceed ±1% to remain within the calibration range
of the current outputs. The current in the resistor is
monitored and the status is indicated in the supervisory
register SPV_REG. When leaving the tolerance range,
it switches to an on-chip generated current. To prevent
voltage drop on the supply line and bond wire at pin RN,
this pin must not be connected externally to ground.
Clock
An adjustable, internal oscillator generates a 2 MHz
clock with a low temperature coefficient. A PLL multi-
plies this by the factor of 8 for use as the µC system
clock. This PLL is also monitored and its status sig-
nalled in the supervisory register SPV_INT.
Calibration
The required calibration values can be transferred to
the iC-GD in two different ways:
1. The calibration values are written via I²C directly
into the EEPROM. These changes are not directly
transfered to the chip and require a restart (chang-
ing the mode will only be sufficed for calibration
data that is reloaded selectively on demand i.e.
AGIAmx, AGFnx, AOFnx).
2. The calibration values are written directly into the
on-chip registers via SPI. Since these registers
are not accessible in regular operation, the cali-
bration mode must be activated. After all required
calibration data have been calculated, they are
also written into the EEPROM.
Calibration mode is activated by the register
SPI_LOCK_RESET. If calibration mode is active, the
internal register addresses used for the SPI communi-
cation differ partly from the valid addresses. If registers
other than the calibration registers must be used, cali-
bration mode must be deactivated again by the register
SPI_LOCK_RESET. The remaining opcodes, including
those for the transmission of process data, remain fully
functional. Table 17 shows the valid internal addresses
for calibration mode.