IC-MB4_15 Datasheet, PDF (37/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
preliminary
Rev B2, Page 37/40
APPLICATION DESIGN TRANSFER FROM iC-MB3 TSSOP24 TO iC-MB4 TSSOP24
In order to transfer iC-MB3 TSSOP24 applications to
iC-MB4 applications the following items need to be ver-
ified:
• Related details on PCB
• Configurations
• Operational sequences
Pin compatibility
As both devices are register and pin compatible^∗ the
iC-MB4 TSSOP24 is a drop in replacement possibility
to iC-MB3 TSSOP24.
All pins keep their function except one pin that typically
was not used by former iC-MB3 TSSOP24 users:
• iC-MB3 TSSOP24:
pin 22: CLKOUT clock output
• iC-MB4 TSSOP24:
pin 22: MO1 BiSS data line output
The internal oscillator of the iC-MB3 TSSOP24 is typ-
ically not used as a clock source. With the updated
MB100_X BiSS master IP the control of the MO line
is possible with iC-MB3 TSSOP24. As most of on the
market available encoder are point-to-point encoder
the signal MO is such applications not required. The
parameter "EN_MO" in address 0xE5; bit 1 controls the
level:
• 0 MO to low
• 1 parameterized processing time by master on MO
signal active (length: MO_BUSY).
In typical point-to-point applications there is no MO at
the sensor required/used and the sensors SLI = 0 (of-
ten constant level inside sensor) = MO (if required and
connected).
BiSS C register access functionality
The iC-MB3 TSSOP24 can only perform BiSS B regis-
ter access with the REGADR, REGNUM, ... , not BiSS
C. To perform BiSS C register access a sequence of
CDM bits for the register access is needed (read or
write) and with the appropriate command (GETSENS0
or GETSENS1) the SCD cycle is triggered, the CDS bit
of this cycle is captured and the CDM bit is output on the
MA line (please check BiSS AN 4). iC-MB3 TSSOP24
with host support support is also BiSS C capable and
designs on iC-MB3 TSSOP24 can be upgraded with
iC-MB4 TSSOP24. iC-MB4 is full BiSS B and BiSS C
register access capable.
Differing operational sequences on BiSS B and
BiSS C register access
The operational sequence to perform a BiSS B register
access differs to the operational sequence to perform
a BiSS C register access. On BiSS B the SCD trans-
fer was stopped and the BiSS B register access was
executed. With BiSS C the SCD transfer is required to
perform the BiSS C register access. Adaptions of an ex-
isting BiSS B register access the operational sequence
for BiSS C register access need to be verified.
Disabeling SCD CRC verification
To deactivate the SCD CRC verification select:
• SELCRCSx = 0b0
• CRC bit length in SCRCLENx = 0 .
• Extend the SCDLEN by the length of the present CRC
that is subject to be ignored.
A CRC polynome SCRCPOLYx = 0x00 is not applicable
with SELCRCSx = 0b1.
Obsolete MCD functions removed
Multi Cycle Data (MCD) functions have completely been
removed in iC-MB4 TSSOP24. This covers functions,
parameters, data and status. Former iC-MB3 TSSOP24
configurations and operational sequences that applied
MCD need to be verified, removed or adapted.
∗ _{Not using CLKOUT as a clock source within application.}