IC-MB4_15 Datasheet, PDF (14/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
preliminary
Rev B2, Page 14/40
OPERATING REQUIREMENTS: BiSS Interface - BiSS Frame
Operating conditions: register bit SELSSI = 0 VDD = 3.0 . . . 5.5 V, Tj = -40 . . . 125 °C
Alias: MA = MA1/MA2_NMA1, SL = SL1/SL2_NSL1
Item Symbol Parameter
No.
Conditions
Sensor Data Cycle
I301 TMAS Clock Period
FreqSens via FREQ(4:0) selected in
accordance with table 45 on page 29
I302 tMASl
Clock Signal Lo Level Duration
I303 tMASh Clock Signal Hi Level Duration
I304 tpLine
I305 ∆ tpL
I306 Ttos
Permissible Line Delay
Permissible Propagation Delay of
∆ tpL = max(|tpLine - tpLx|); x= 1 ... n
Subsequent Clock Cycles vs. 1st Clock
Cycle
Permissible Timeout (Slave)
Min.
Unit
Max.
2
320 1/f(CLK)
50
50
%
TMAS
50
50
%
TMAS
0 indefinite
25
%
TMAS
55
%
TMAS
SLx line sampling
Figure 8: Timing diagram BiSS Frame
With BiSS line delays longer than one clock cycle are permissible, with the result that line delays during
communication are negligible. The evaluation of the sensor response is delayed until the first falling edge at SLx
while the clock signal continues to be output at MAx .
Within one MAx clock cycle four equally distributed sampling instances are available. Following the falling edge at
SLx is the slaves acknowledge signal. The SL1 level is evaluated by two sampling instances, close to the center
of the transmitted bit.