IC-MB4_15 Datasheet, PDF (30/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
preliminary
Rev B2, Page 30/40
cess is similar to BiSS C and can be operated down to
80 kHz.
The FREQAGS controls the automatic SCD timing. Au-
tomatic SCD timings are enabled by the instruction bit
AGS. With FREQAGS the cycle rate can be set to a
dedicated ratio of the f_CLK. For the fastest possible cy-
cle rate FREQAGS is set to AGSMIN. For the cycle rate
that is controlled externally by GETSENS, FREQAGS
is set to AGSINFINITE.
With an external clock of 20 MHz sensor data request
cycles ranging from 1 µs to 4 ms are possible. FRE-
QAGS must be set in a way that the distance between
two requests for data is greater than a complete cy-
cle; this consists of the transmission of a request, an
acknowledge signal (including any line delays), a start
bit (including process times), a register bit (optional),
the sensor and CRC bits of each slave and the longest
sensor timeout of all the slaves.
FREQAGS
Addr. 0xE8; bit 7:0
R/W
0x00 . .
0x7B
f_CLK/ (20 * (FREQAGS(6:0)+1) )
0x7C
AGSMIN
0x7D . .
0x7F
AGSINFINITE
0x80 . .
0xFF
f_CLK/ (625 * (FREQAGS(6:0)+1) )
Table 46: AutoGetSens frequency
AGSMIN
With AGSMIN the master automatically restarts the
next cycle after the prior was finished. AGSMIN is the
fastest SCD rate with complete SCD cycles. The rate
depends on the configured master clock frequency, the
total slave configuration, slaves processing time and
the total system line delay.
AGSINFINITE
With AGSINFINITE the master does not automatically
restart the next cycle after the prior one was finished.
AGSINFINITE requires a trigger event to start the next
SCD cycle. Possible trigger events are a GETSENS
signal or an INST instruction that start a cycle.
The buffering of the received SCD and the access to
the SCD can use two or one RAM bank. When using
only a single RAM bank, the access to prior SCD needs
to be coordinated with a possible update of new SCD.
SINGLEBANK
Addr. 0xE7; bit 1
R/W
0
Two RAM banks are used for SCD
1
One RAM bank is used for SCD
Table 48: Usage of single RAM bank for SCD
BiSS Master Device Identification
The BiSS master device is identifiable with the two
register VERSION and REVISION. A host software can
use VERSION and REVISION to identify the present
device and verify the compatibility of software and
device.
VERSION
Addr. 0xEB; bit 7:0
R
0x83
iC-MB3
0x84
iC-MB4
...
...
0xFF
Table 49: iC-MB version
REVISION
Addr. 0xEA; bit 7:0
R
0x10
Z(first revision)
0x11
Z1
0x20
Y
...
0xFF
Table 50: iC-MBx redesign ID
The MB100 BiSS IP´s do also provide a version and
revision for identification.
The RAM location for the received and processed CRC
bits are the most significant bits each slaves SCDATA.
VERSION
Addr. 0xEB; bit 7:0
R
0x41
BiSS IP MB101
NOCRC
0
Addr. 0xE7; bit 1
R/W
CRC of SCD is stored RAM (only applicable with
active CRC verification and CRC polynome > 0)
...
0x49
...
...
BiSS IP MB109
...
1
CRC of SCD not to be stored in RAM
0x82
Table 47: All Slave CRC RAM copy
Table 51: MB100 version