IC-MB4_15 Datasheet, PDF (19/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
preliminary
OVERVIEW
Addr
Bit 7
Bit 6
Slave Configuration 2
0xEF
Status Information
0xF0
nERR
nAGSERR
0xF1
SVALID4
’0’
0xF2
SVALID8
’0’
0xF3
CDMTIME-
OUT
CDSSEL
Instruction Register
0xF4
BREAK
HOLDBANK
0xF5
MAVO
MAFO
0xF6
–
–
0xF7
–
–
Status Information 2
0xF8
0
1
0xF9
0
1
0xFA
–
–
0xFB
–
–
Bit 5
nDELAYERR
SVALID3
SVALID7
SWBANK
MAVS
–
–
0
0
–
–
Bit 4
Bit 3
Bit 2
ACTnSENS(8:1)
nSCDERR
’0’
’0’
nREGERR REGEND
SVALID2
’0’
SVALID6
’0’
REGBYTES(5:0)
INIT
MAFS
–
–
1
1
–
–
INSTR(2:0)
CFGIF(1:0)
–
–
–
–
CDS2
SL2
0
1
–
–
–
–
Reserved
0xFC . .
–
–
–
–
–
–
0xFF
Rev B2, Page 19/40
Bit 1
Bit 0
’1’
SVALID1
SVALID5
EOT
’0’
’0’
ENTEST
–
–
AGS
CLKENI
–
–
CDS1
0
–
–
SL1
1
–
SWBANK-
FAILS
–
–
Table 10: Register layout
iC-MB4 does reset all RAM registers to 0 on a
power on reset.