IC-MB4_15 Datasheet, PDF (15/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
preliminary
Rev B2, Page 15/40
OPERATING REQUIREMENTS: BiSS Interface - Register Data Cycle (BiSS B)
Operating conditions: register bit SELSSI = 0 VDD = 3.0. . . 5.5 V, Tj = -40. . . 125 °C
Alias: MA = MA1/MA2_NMA1, SL = SL1/SL2_NSL1
Item Symbol Parameter
No.
Conditions
Your copied rows:
I401 TMAR Clock Period
FreqReg via FREQ(7:5) selected in
accordance with table on page XXX
I402 tMA0h ”Logic 0” Hi Level Duration
I403 tMA1h ”Logic 1” Hi Level Duration
I404 tMAth
Clock Signal Hi Level Duration
register data readout
I405 tsSM
I406 thSM
I407 Ttor
Setup Time: SL stable before MA lo→hi
Hold Time: SL stable after MA lo→hi
Permissible Timeout (Slave)
Min.
2
25
75
50
30
0
80
Unit
Max.
256 TMAS
25
%
TMAR
75
%
TMAR
50
%
TMAR
ns
ns
%
TMAR
Figure 9: Timing diagram BiSS B register access