IC-MB4_15 Datasheet, PDF (18/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
REGISTER LAYOUT, OVERVIEW
preliminary
Rev B2, Page 18/40
OVERVIEW
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Sensor and Actuator Data
0x00
SCDATA1(7:0)
0x01 . .
0x07
SCDATA1(63:8)
0x08 . .
0x3F
0x40 . .
0x7F
SCDATA2(63:0) . . SCDATA8(63:0)
–^∗
Register Data
0x80 ^†
0x80 ^‡
RDATA1(7:0)
IDS(7:0)
0x81 . .
0xBF
RDATA2(7:0) . . RDATA64(7:0)
Configuration Slave 1
0xC0
GRAYS1 /
LSTOP1
ENSCD1
SCDLEN1(5:0)
0xC1
SELCRCS1
SCRCLEN1(6:0) / SCRCPOLY1(7:1)
0xC2
SCRCSTART1(7:0)
0xC3
SCRCSTART1(15:8)
0xC4 . .
0xDF
Configuration Slave 2(31:0) . . Configuration Slave 8(31:0)
Control Communication Configuration
0xE0
–^∗
0xE1
–^∗
0xE2
0xE3
0xE4
0xE5 ^†
0xE5 ^‡
WNR
–^∗
CTS
CTS
REGVERS
REGVERS
REGADR(6:0)
REGNUM(5:0)
–^∗
SLAVEID(2:0)
–^∗
CMD(1:0)
IDA_TEST
–^∗
Master Configuration
0xE6
0xE7
FREQR(2:0)
–^∗
FREQS(4:0)
0xE8
FREQAGS(7:0)
0xE9
0xEA
0xEB
MO_BUSY(7:0)
REVISION(7:0)^§
VERSION(7:0)^§
Channel Configuration
0xEC
’0’
0xED
0xEE
’0’
’0’
–^∗
SLAVELOC5
–^∗
’0’
’0’
CFGCH2(1:0)
Bit 1
Bit 0
CHSEL(2:1)
EN_MO
HOLDCDM
EN_MO
HOLDCDM
NOCRC SINGLEBANK
’0’
’1’
CFGCH1(1:0)
∗ _{Reserved or unused register bits highlighted as ”–” need to be written with 0 if a byte wide register write access is required.}
† _{Using register access in control communication.}
‡ _{Using command/instructions in control communication.}
§ _{Register bits with constant ”0” or ”1” are ROM-based values and can not be changed through writing.}