IC-MB4_15 Datasheet, PDF (17/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
PROGRAMMING
preliminary
Rev B2, Page 17/40
Register Layout, Overview . . . . . . . . . . . . . . . . Page 18
Sensor Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 24
SCDATAx:
Single cycle data (SCD)
(sensor resp. actuator data, 64 bit per
slave, 2 banks)
Register Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 26
RDATAx:
Register data (64 byte)
Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . Page 32
SCDLENx: Single cycle data length
ENSCDx:
Enable single cycle data
GRAYSx:
Enable SCD gray to binary conversion
(SSI only)
SCRCPOLYx: Polynomial for SCD CRC check
SCRCLENx: Polynomial selection by length for SCD
CRC check
SELCRCSx: Selection between polynomial or
length for SCD CRC polynomial
SCRCSTARTx: Start value for polynomial SCD CRC
calculation
Control Communication Configuration . . . Page 26
REGADR:
WNR:
REGNUM:
CHSEL:
SLAVEID:
REGVERS:
CTS:
HOLDCDM:
EN_MO:
Register address
Read/write selector
Register data count
Channel selector
Slave selector
BiSS model A/B or C selector
Register transmission or instruction se-
lector
Hold CDM (control data master)
Enable output at MOx for actuator data
or delayed start bit
Master Configuration . . . . . . . . . . . . . . . . . . . . . Page 29
FREQS:
Frequency division
FREQR:
Frequency division register communi-
cation BiSS B
FRGAGS: AutoGetSens Frequency division
REVISION: Revision
VERSION: Device identifier
SINGLEBANK: Use of only one RAM bank for SCD
NOCRC:
CRC for SCD not to be stored in RAM
MOBUSY: Delay of start bit at output MOx
Channel Configuration . . . . . . . . . . . . . . . . . . . Page 32
SLAVELOC: Slave location
CHCFGx: Channel configuration
ACTnSENS: Sensor or actuator data selector
Status Information . . . . . . . . . . . . . . . . . . . . . . . . Page 35
EOT:
Data transmission completed
nERR:
Error at NER pin
REGEND: Register data transmission completed
nREGERR: Error in register data transmission
nSCDERR: Error in single cycle data transmission
nDELAYERR: Missing start bit during register com-
munication
nAGSERR: Unable to start SCD frame
SVALIDx:
Single cycle data valid
REGBYTES: Number of valid register data transmit-
ted in case of error
CDSSEL:
Register bit of data transmission (se-
lected channel)
CDMTIME- Control data timeout met
OUT:
Instruction Register . . . . . . . . . . . . . . . . . . . . . . . Page 28
INSTR:
AGS:
INIT:
SWBANK:
HOLDBANK:
BREAK:
CLKENI:
ENTEST:
CFGIF:
MAFS:
MAVS:
MAFO:
MAVO:
Instruction
AutoGetSens
Initialize
Switch RAM banks
Inhibit RAM bank switching
Data transmission interrupt
Enable internal clock
Enable test interface
Configure physical interfaces
Master line control (selected channel)
Master line control (selected channel)
Master line control (deselected chan-
nel)
Master line control (deselected chan-
nel)
Status Information 2 . . . . . . . . . . . . . . . . . . . . . . Page 36
SLx:
CDSx:
SWBANK-
FAILS:
Current SL line level
Control data bit slave
Bank switching for single cycle data
failed