IC-MB4_15 Datasheet, PDF (36/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
preliminary
Rev B2, Page 36/40
SVALID1
SVALID2
SVALID3
SVALID4
SVALID5
SVALID6
SVALID7
SVALID8
0
1
Addr. 0xF1; bit 1
Addr. 0xF1; bit 3
Addr. 0xF1; bit 5
Addr. 0xF1; bit 7
Addr. 0xF2; bit 1
Addr. 0xF2; bit 3
Addr. 0xF2; bit 5
Addr. 0xF2; bit 7
SCD invalid
SCD valid
R/W - 0
R/W - 0
R/W - 0
R/W - 0
R/W - 0
R/W - 0
R/W - 0
R/W - 0
communication by host control. Therefore the CDM-
TIMEOUT bit indicates that ≥ 14 SCD cycles with
CDM = 0 have been sent before.
CDMTIMEOUT
(Register vaild)
Addr. 0xF3; bit 7
0
CDMTIMEOUT not reached
1
CDMTIMEOUT reached
Table 74: CDM timeout reached
R-1
Table 73: SCDATAx validity indication
With BiSS C register communication the count of SCD
cycles with CDM = 0 is relevant for a manual register
CDSSEL
Addr. 0xF3; bit 6
CDS from the selected channel
R-1
Table 75: CDS bit from the selected channel
STATUS INFORMATION 2
SL1
SL2
SL3^∗
SL4^∗
SL5^∗
SL6^∗
SL7^∗
SL8^∗
0
1
Addr. 0xF8; bit 0
Addr. 0xF8; bit 2
Addr. 0xF8; bit 4
Addr. 0xF8; bit 6
Addr. 0xF9; bit 0
Addr. 0xF9; bit 2
Addr. 0xF9; bit 4
Addr. 0xF9; bit 6
SL line level low
SL line level high
Table 76: SL input line state
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
CDS1
CDS2
CDS3^†
CDS4^†
CDS5^†
CDS6^†
CDS7^†
CDS8^†
0
1
Addr. 0xF8; bit 1
Addr. 0xF8; bit 3
Addr. 0xF8; bit 5
Addr. 0xF8; bit 7
Addr. 0xF9; bit 1
Addr. 0xF9; bit 3
Addr. 0xF9; bit 5
Addr. 0xF9; bit 7
CDS = 0
CDS = 1
Table 77: CDS bit of channel
SWBANKFAILS
Bank switching
SCD not
successful
Addr. 0xFB; bit 0
0
Bank switching (SCD) successful
1
Bank switching (SCD) not successful
Table 78: Bank switching status
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
∗ _{SL3 . . . SL8 are not available with iC-MB4.}
† _{CDS3 . . . CDS8 are not available with iC-MB4.}