IC-MB4_15 Datasheet, PDF (20/40 Pages) IC-Haus GmbH – BiSS INTERFACE MASTER

iC-MB4
BiSS INTERFACE MASTER
FUNCTIONAL DESCRIPTION
preliminary
Rev B2, Page 20/40
BiSS C Frame
BiSS uses in the point-to-point configuration a clock
line (MA) from the master to the slave and a data line
(SL) from the slave to the master. A device may contain
multiple slaves. The data input (SLI) of the last slave
is set to low, the slaves are daisychained (SLO → SLI),
and the data output (SLO) of the first slave is directed
to the master. A data line from the master to the slave
is not mandatory (see figure 1).
At the end of the cycle the master sends the CDM bit
(inverted) on the MA clock line. After detecting the
slaves timeout with SLO = 1 the master changes the
MA clock line state to high. If the BiSS frame has not
been clocked out finally, e.g. for a faster configuration
phase and higher control data transmission rates, the
HOLDCDM needs to be enabled to keep the clock line
constant until the next cycle starts. The difference is
explained in figures 11 and 12.
BiSS C provides the additional bus configuration with
the data output line (MO) from the master to the slaves.
With EN_MO = 1 the master emulates a slave without
sensor data at the MO line. The parameterized pro-
cessing time for sensor data (i.e. the ”start bit delay”) is
configured by the MO_BUSY parameter.
Figure 11: BiSS frame in point-to-point configuration (EN_MO = 0, HOLDCDM = 0)
Figure 12: BiSS frame in bus configuration (EN_MO = 1, HOLDCDM = 1)
BiSS B Register Communication
In BiSS B the register communication is started by a
timing condition and a handshake at the beginning of
the cycle (see figure 13). Alternatively the register com-
munication can be selected at the cycle start with the
MO line. With EN_MO = 1 the slave ID ”0” remains
unused.
Figure 13: BiSS B register access (EN_MO = 0)