IC-MH16_15 Datasheet, PDF (20/25 Pages) IC-Haus GmbH – 12-BIT ANGULAR HALL ENCODER

iC-MH16
12-BIT ANGULAR HALL ENCODER
preliminary
PCOS
PSIN
U
V
W
U
V
W
U
V
W
Figure 21: UVW signals for different settings of CFG-
COM
Rev A1, Page 20/25
For an autonomous and torque optimized motor com-
mutation it is recommended, to deactivate the synchro-
nization with the parameter DCS.
DCS
0
1
Addr. 0x5; bit 7
Commutation signal synchronization enabled
Commutation signal synchronization disabled
Table 24: Synchronization of commutation signals
After changing the direction of rotation, the commuta-
tion signal which appears within 0.7 ° after the reversal
point is shifted; the distance between two consecutive
transitions is max. 0.7 ° shorter. At constant direction
no systematical error occurs.
CFGCOM(1:0)
Addr. 0x9; bit 7:4
0x0
1 pole pair commutation
0x1
2 pole pair commutation
...
...
0xF
16 pole pair commutation
Table 23: Commutation
The commutation signals, which has a much shorter
latency, are synchronized to the sine/digital converter.
Figure 22: Hysteresis for UVW signals
OUTPUT DRIVERS
Three RS422-compatible output drivers for the incre-
mental signals A - NA, B - NB and Z - NZ are available.
The property of the RS422 driver of the connected line
can be adjusted in the CFGDR register.
CFGDR(1:0)
Addr. 0x05; bit 1:0
0x00
10 MHz 4 mA (default)
0x01
10 MHz 60 mA
0x10
300 kHz 60 mA
0x11
3 MHz 20 mA
Table 25: Driver property for incremental signals
line over a short distance. Steep edges on the output
enable a high transmission rate. A lower slew rate is
offered by the setting CFGDR = 0x10, which is excel-
lent for longer lines in an electromagnetically sensitive
environment. Use of the setting CFGDR = 0x11 is advis-
able at medium transmission rates with a limited driver
capability.
TRIHL
0x00
0x01
0x10
0x11
Addr. 0x05; bit 3:2
Push, pull output stage
Highside driver
Lowside driver
Tristate
Signals with the highest frequency can be transmitted
in the setting CFGDR = 0x00. The driver capability is
at least 4 mA, however it is not designed for a 100 Ω
line. This mode is ideal for connection to a digital in-
put on the same assembly. With the setting CFGDR =
0x01 the same transmission speed is available and
the driver power is sufficient for the connection of a
Table 26: Tristate Register for incremental signals
The drivers consist of a push-pull stage in each case
with low-side and high-side drivers which can each be
activated individually. As a result, open-drain outputs
with an external pull-up resistor can also be realized.