IC-MH16_15 Datasheet, PDF (19/25 Pages) IC-Haus GmbH – 12-BIT ANGULAR HALL ENCODER

iC-MH16
12-BIT ANGULAR HALL ENCODER
preliminary
Rev A1, Page 19/25
5°
0°
−5°
A
B
Z
0°



















¡
0°
CFGDIR
0
1
Addr. 0x07; bit 5
Rotating direction CCW
Rotating direction CW
Table 21: Rotating direction reversal
Figure 20: Quadrature signals for rotating direction
reversal with hysteresis (CFGDIR = 0)
At the reversal point at +10 °, first the corresponding
edge is generated at A. As soon as an angle according
to the hysteresis has been exceeded in the other direc-
tion, the return edge is generated at A again first. This
means that all edges are shifted by the same value in
the rotating direction.
The rotating direction can easily be changed with the bit
CFGDIR. When the setting is CCW (counter-clockwise,
CFGDIR = 0x0) the resulting angular position values
will increase when rotation of the magnet is performed
as shown in Figure 6. To obtain increasing angular po-
sition values in the CW (clockwise) direction, CFGDIR
then has to be set to 0x1.
CFGZPOS(7:0) Addr. 0x08; bit 7:0
CFGZPOS(11:8) Addr. 0x09; bit 3:0
0x0
0°
0x1
0.08 °
0x2
0.16 °
...
360
4096
·CFGZPos
0xff
359.9 °
The internal analog sine and cosine signal which are
available in test mode are not affected by the setting of
CFGDIR. They will always appear as shown in Figure
6.
Table 19: Programming zero position
The zero position can be set in 0.08 ° steps. It is valid
for the quadrature and commutation signals. An 12-bit
register is provided for this purpose, which can shift the
Z-pulse once over 360 °.
CFGSU
0
1
Addr. 0x07; bit 4
ABZ output "111" during startup
AB instantly counting to actual position
Table 22: Configuration of output startup
CFGMTD(1:0)
Addr. 0x05; bit 5:4
0
62.5 ns
1
125 ns
2
500 ns
3
2 µs
Table 20: Minimum edge spacing
The CFGMTD register defines the time in which two
consecutive position events can be output at the highest
resolution. The default is a maximum output frequency
of 500 kHz on A. This means that at the highest resolu-
tion, speeds of 25 000 rpms can still be correctly shown.
In the setting with an edge spacing of 62.5 ns, the edges
can be generated even at the highest revolution and the
maximum speed. However, the counter connected to
the module must be able to correctly process all edges
in this case. The settings with 2 µs can be used for
slower counters. It should be noted then, however, that
the maximum rotation speed is reduced.
Depending on the application, a counter cannot bear
generated pulses while the module is being switched on.
When the supply voltage is being connected, first the
current position is determined. During this phase, the
quadrature outputs are constantly set to "111". In the
setting CFGSU = 0x1, edges are generated at the out-
put until the absolute position is reached. This enables
a detection of the absolute position with the incremental
interface.
The converter for the generation of the commutation
signals can be configured for up to 16 pole pair motors.
Three rectangular signals each with a phase shift of
120 ° are generated. With a two pole pair setting, the
commutation sequence is generated twice per rotation.