GDC21D301A Datasheet, PDF (8/35 Pages) Hynix Semiconductor – Transport Decoder

GDC21D301A
Pin Description (continued)
NAME
\DSP_STRB
DSP_RWB
\DSP_PD
DSP_ADDR[22:0]
BIT8MODE
DSP_DATA[15:0]
DSP_READY
DSP_INT
PIN
TYPE
DESCRIPTION
HOST PROCESSOR INTERFACE
127
I
Host Strobe (active low) : Asynchronous.
Used by the host processor to access the GDC21D301A. When
DSP_STRB signal is active, DSP_ADDR[22:0],
DSP_DATA[15:0], and DSP_PD should be valid.
128
I
Read/Write (active low) : Asynchronous.
The state of this signal defines data transfer type.
0 : Write to the device 1: Read from the device
129
I
Transport Decoder Chip Selection (active low).
This signal is used to activate and access the internal registers
of the GDC21D301A, the video decoder, the audio decoder, the
data decoder, and DRAM.
133,134,135,
I
Host Address Bus.
136,137,138,
These signals are connected to the address bus of the host
139,140,141,
processor interfaced with the GDC21D301A, the video
142,143,144,
decoder, the audio decoder, the data decoder, and DRAM.
145,146,147,
0x4FFFFF ~ 0x4C0000 : Transport Decoder address space
148,149,150,
0x5BFFFF ~ 0x480000 : Video decoder space
151,152,153,
0x47FFFF ~ 0x440000 : Audio decoder space
154,155
0x43FFFF ~ 0x400000 : Auxiliary data decoder space
0x3FFFFF ~ 0x000000 : DRAM space
156
I
Host Interface Mode Selection.
0 : 16-bit data bus interface
1 : 8-bit data bus interface
3, 2, 1, 176, I/O/Z Host Data Bus.
174,173,172,
These signals are connected to the address bus of external host
171,169,168,
processor.
167,166,164,
163,162,161
6
O/Z Data Acknowledge (active high)
5
O Interrupt Request (active high)
9