GDC21D301A Datasheet, PDF (16/35 Pages) Hynix Semiconductor – Transport Decoder

Interrupt Flag 2 (0x002)
When an interrupt condition occurs, the
corresponding bit in Interrupt Flag registers are
asserted 1. Whenever a bit in the Interrupt Flag is 1,
the corresponding bit in Interrupt Mask registers is
set to 1, the Ien bit in the Instruction register to 1,
and the GDC21D301A asserts DSP_INT, the
external interrupt signal. Note that the occurrence
of an interrupt condition always causes the
corresponding bit in Interrupt Flag registers to be
set, even if the condition is disabled(i.e., the
corresponding bit in Interrupt Mask registers is
set to 0).
Interrupt Flag 1, 2 registers are cleared by the
GDC21D301A
Host whenever they are read, and DSP_INT is
deasserted.
In the GDC21D301A, Slk and Sdr is added to
indicate the state of Sync. The GDC21D301A first
searches Sync byte from transport stream. If the
device succeeds in finding 0x47, it writes
Slk(Sync_lock) bit in Interrupt flag 2 register. Until
sync is detected, Sdr flag maintains active high
state, so the host processor can monitor whether
Sync(0x47) is detected or not.
All bits except Slk and Sdr are set when packet is
matched to PID register.
15
87
Slk Sdr Psc Ppr Dai Cpr Ooc Pdf
FIELD
Slk
Sdr
Psc
Ppr
Dai
Cpr
Ooc
Pdf
Esf
Erf
Dtf
Acf
Crf
Pef
BITS
15
14
13:12
11
10
9
8
7:6
5
4
3
2
1
0
DESCRIPTION
Sync_lock
Sync_drop
PES_scrambling_control
PES_priority
data_alignment_indicator
copyright
original_or_copy
PTS_DTS_flag
ESCR_flag
ES_rate_flag
DSM_trick_mode_flag
additional_copy_info_flag
PES_CRC_flag
PES_extension_flag
0
Esf Erf Dtf Acf Crf Pef
VALUES
DEFAULT
Interrupt Mask 1 (0x004)
All bits respectively correspond with each ones in
Interrupt Flag 1 register.
1 = Interrupt enabled
Interrupt Mask 2 (0x006)
All bits respectively correspond with each ones in
Interrupt Flag 2 register.
1 = Interrupt enabled
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